| Line 72... |
Line 72... |
rd_rq <= 0;
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rd_rq <= 0;
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wr_rq <= 0;
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wr_rq <= 0;
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end
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end
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else
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else
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begin
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begin
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if ( ((s00_AXI_AWVALID == 1) && (s00_AXI_AWREADY ==0)) ) begin s00_AXI_AWREADY <=1; wadd <= s00_AXI_AWADDR[16:2]; end else
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if ( ((s00_AXI_AWVALID == 1) && (s00_AXI_AWREADY ==0)) ) begin s00_AXI_AWREADY <=1; wadd <= s00_AXI_AWADDR[16:2]; end
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if ( ((s00_AXI_ARVALID == 1) && (s00_AXI_ARREADY ==0)) ) begin rd_rq <= 1; s00_AXI_ARREADY <=1; radd <= s00_AXI_ARADDR[16:2]; end else
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if ( ((s00_AXI_ARVALID == 1) && (s00_AXI_ARREADY ==0)) ) begin rd_rq <= 1; s00_AXI_ARREADY <=1; radd <= s00_AXI_ARADDR[16:2]; end else
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begin
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begin
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s00_AXI_ARREADY <=0;
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s00_AXI_ARREADY <=0;
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s00_AXI_AWREADY <=0;
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s00_AXI_AWREADY <=0;
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if (rd_gnt ==1)
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begin
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rd_rq <=0;
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s00_AXI_RVALID <= 1;
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s00_AXI_RLAST <= 1;
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end
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else
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begin
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s00_AXI_RVALID <= 0;
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s00_AXI_RLAST <= 1;
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end
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end
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end
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if ( wr_gnt == 1) begin s00_AXI_WREADY <=1; wr_rq <=0; wr_strb <= 0; end else
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if ( wr_gnt == 1) begin s00_AXI_WREADY <=1; wr_rq <=0; wr_strb <= 0; end else
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if ((s00_AXI_WVALID == 1) && (s00_AXI_WREADY ==0)) begin wr_rq <= 1; wr_strb <= s00_AXI_WSTRB; wdat <= s00_AXI_WDATA; end else
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if ((s00_AXI_WVALID == 1) && (s00_AXI_WREADY ==0)) begin wr_rq <= 1; wr_strb <= s00_AXI_WSTRB; wdat <= s00_AXI_WDATA; end else
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s00_AXI_WREADY <=0;
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s00_AXI_WREADY <=0;
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if (rd_gnt ==1) begin s00_AXI_RDATA <= {Qreg1,Qreg2,Qreg3,Qreg4}; s00_AXI_RVALID <=1; end else s00_AXI_RVALID <=0;
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end
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end
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// clock divider gap
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// clock divider gap
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| Line 99... |
Line 112... |
gadd <=0;
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gadd <=0;
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fifo <=0;
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fifo <=0;
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rd_gnt <= 0;
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rd_gnt <= 0;
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wr_gnt <= 0;
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wr_gnt <= 0;
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vadd <=0;
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vadd <=0;
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s00_AXI_RDATA <=0;
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end
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end
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else
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else
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begin
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begin
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if ((gclk == 0) && (wr_rq ==1)) begin wr_gnt <= 1; vadd <= wadd; {wreq1,wreq2,wreq3,wreq4} <= wr_strb; end else
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if ((gclk == 0) && (wr_rq ==1)) begin wr_gnt <= 1; vadd <= wadd; {wreq1,wreq2,wreq3,wreq4} <= wr_strb; end else
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if ((gclk == 0) && (rd_rq ==1)) begin vadd <= radd; end else
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if ((gclk == 0) && (rd_rq ==1)) begin vadd <= radd; end else
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if ((gclk == 1) && (wr_rq ==1)) begin {wreq1,wreq2,wreq3,wreq4} <= 0; vadd <= gadd; end else
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if ((gclk == 1) && (wr_rq ==1)) begin {wreq1,wreq2,wreq3,wreq4} <= 0; vadd <= gadd; end else
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if ((gclk == 1) && (rd_rq ==1)) begin rd_gnt <= 1; vadd <= gadd; end else
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if ((gclk == 1) && (rd_rq ==1)) begin rd_gnt <= 1; vadd <= gadd; end else
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if (gclk == 1) begin vadd <= gadd; end else
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if (gclk == 1) begin vadd <= gadd; end else
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if (gclk == 2) begin wr_gnt <=0; rd_gnt <=0; end
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if (gclk == 2) begin wr_gnt <=0; rd_gnt <=0; s00_AXI_RDATA <= {Qreg1,Qreg2,Qreg3,Qreg4}; end
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// update video address
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// update video address
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if ((counY < 10'd400) && (nextcounX <10'd640)) gadd <=nextcounX[9:2]+{counY[9:1],7'b0}+{counY[9:1],5'b0};
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if ((counY < 10'd400) && (nextcounX <10'd640)) gadd <=nextcounX[9:2]+{counY[9:1],7'b0}+{counY[9:1],5'b0};
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if (gclk == 3) fifo <= {Qreg1,Qreg2,Qreg3,Qreg4};
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if (gclk == 3) fifo <= {Qreg1,Qreg2,Qreg3,Qreg4};
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end
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end
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