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[/] [biriscv/] [trunk/] [README.md] - Diff between revs 2 and 4
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*A sequence showing execution of 2 instructions per cycle;*
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*A sequence showing execution of 2 instructions per cycle;*
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![Dual-Issue](docs/dual_issue.png)
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![Dual-Issue](docs/dual_issue.png)
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## Documentation
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## Documentation
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* [Configuration](http://github.com/ultraembedded/biriscv/docs/configuration.md)
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* [Configuration](https://github.com/ultraembedded/biriscv/blob/master/docs/configuration.md)
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* [Booting Linux](http://github.com/ultraembedded/biriscv/docs/linux.md)
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* [Booting Linux](https://github.com/ultraembedded/biriscv/blob/master/docs/linux.md)
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* [Integration](http://github.com/ultraembedded/biriscv/docs/integration.md)
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* [Integration](https://github.com/ultraembedded/biriscv/blob/master/docs/integration.md)
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* [Custom Features](http://github.com/ultraembedded/biriscv/docs/custom.md)
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* [Custom Features](https://github.com/ultraembedded/biriscv/blob/master/docs/custom.md)
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## Similar Cores
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## Similar Cores
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* [SiFive E76](https://www.sifive.com/cores/e76)
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* [SiFive E76](https://www.sifive.com/cores/e76)
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* RV32IMAFC
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* RV32IMAFC
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* Dual issue in-order 8 stage pipeline
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* Dual issue in-order 8 stage pipeline
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