URL https://opencores.org/ocsvn/bluespec-h264/bluespec-h264/trunk

Subversion Repositories bluespec-h264

[/] [bluespec-h264/] [trunk/] [dc/] [Makefile] - Diff between revs 30 and 31

Rev 30	Rev 31
Line 1...	Line 1...
`#=======================================================================`	`#=======================================================================`
`# 6.375 Makefile for dc-synth`	`# 6.375 Makefile for dc-synth`
`#-----------------------------------------------------------------------`	`#-----------------------------------------------------------------------`
`# $Id: Makefile,v 1.1 2008-06-26 17:58:25 jamey.hicks Exp $`	`# $Id: Makefile,v 1.2 2008-06-26 17:58:29 jamey.hicks Exp $`
`#`	`#`
`# This makefile will use Synopsys Design Compiler to synthesize`	`# This makefile will use Synopsys Design Compiler to synthesize`
`# your RTL into a gate-level verilog netlist.`	`# your RTL into a gate-level verilog netlist.`
`#`	`#`

Line 42...	Line 42...
`$(bsrcdir)/mkCalc_nC.v \`	`$(bsrcdir)/mkCalc_nC.v \`
`$(bsrcdir)/mkInverseTrans.v \`	`$(bsrcdir)/mkInverseTrans.v \`
`$(bsrcdir)/mkPrediction.v \`	`$(bsrcdir)/mkPrediction.v \`
`$(bsrcdir)/mkDeblockFilter.v \`	`$(bsrcdir)/mkDeblockFilter.v \`
`$(bsrcdir)/mkBufferControl.v \`	`$(bsrcdir)/mkBufferControl.v \`
	`$(bsrcdir)/mkInterpolator.v \`
	`$(bsrcdir)/mkbSVector.v \`
`$(bsrcdir)/mkLeftVector.v \`	`$(bsrcdir)/mkLeftVector.v \`
`$(bsrcdir)/mkTopVector.v \`	`$(bsrcdir)/mkTopVector.v \`
`$(bsrcdir)/mkWorkVectorHor.v \`	`$(bsrcdir)/mkWorkVectorHor.v \`
`$(bsrcdir)/mkWorkVectorVer.v \`	`$(bsrcdir)/mkWorkVectorVer.v \`
`$(bsrcdir)/module_cavlc_coeff_token.v \`	`$(bsrcdir)/module_cavlc_coeff_token.v \`