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[/] [brisc/] [trunk/] [mux4.v] - Diff between revs 2 and 3
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module mux4( mux_out, data_0, data_1, data_2, data_3, select);
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parameter dw = 32;
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input [dw-1:0] data_3, data_2, data_1, data_0;
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input [1:0] select;
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output reg [dw-1:0] mux_out;
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// choose between the four inputs
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always @ ( data_3 or data_2 or data_1 or data_0 or select)
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case (select)// (* synthesis parallel_case *)
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2'd0: mux_out = data_0;
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2'd1: mux_out = data_1;
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2'd2: mux_out = data_2;
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2'd3: mux_out = data_3;
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default: mux_out = {dw{1'bx}};
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endcase
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endmodule
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