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/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used *
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* solely for design, simulation, implementation and creation of *
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* design files limited to Xilinx devices or technologies. Use *
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* with non-Xilinx devices or technologies is expressly prohibited *
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* and immediately terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
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* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
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* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
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* FOR A PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support *
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* appliances, devices, or systems. Use in such applications are *
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* expressly prohibited. *
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* *
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* (c) Copyright 1995-2006 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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// The synopsys directives "translate_off/translate_on" specified below are
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// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
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// tools. Ensure they are correct for your synthesis tool(s).
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// You must compile the wrapper file prog_mem.v when simulating
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// the core, prog_mem. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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`timescale 1ns/1ps
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module prog_mem(
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addr,
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clk,
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dout);
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input [7 : 0] addr;
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input clk;
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output [47 : 0] dout;
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// synopsys translate_off
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BLKMEMSP_V6_2 #(
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8, // c_addr_width
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"0", // c_default_data
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256, // c_depth
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0, // c_enable_rlocs
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0, // c_has_default_data
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0, // c_has_din
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0, // c_has_en
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0, // c_has_limit_data_pitch
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0, // c_has_nd
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0, // c_has_rdy
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0, // c_has_rfd
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0, // c_has_sinit
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0, // c_has_we
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18, // c_limit_data_pitch
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"prog_mem.mif", // c_mem_init_file
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0, // c_pipe_stages
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0, // c_reg_inputs
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"0", // c_sinit_value
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48, // c_width
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0, // c_write_mode
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"0", // c_ybottom_addr
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1, // c_yclk_is_rising
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1, // c_yen_is_high
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"hierarchy1", // c_yhierarchy
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0, // c_ymake_bmm
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"16kx1", // c_yprimitive_type
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1, // c_ysinit_is_high
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"1024", // c_ytop_addr
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0, // c_yuse_single_primitive
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1, // c_ywe_is_high
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1) // c_yydisable_warnings
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inst (
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.ADDR(addr),
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.CLK(clk),
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.DOUT(dout),
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.DIN(),
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.EN(),
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.ND(),
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.RFD(),
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.RDY(),
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.SINIT(),
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.WE());
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// synopsys translate_on
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// FPGA Express black box declaration
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// synopsys attribute fpga_dont_touch "true"
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// synthesis attribute fpga_dont_touch of prog_mem is "true"
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// XST black box declaration
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// box_type "black_box"
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// synthesis attribute box_type of prog_mem is "black_box"
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endmodule
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No newline at end of file
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No newline at end of file
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