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/*******************************************************************************

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*     (c) Copyright 1995-2006 Xilinx, Inc.                                     *

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*******************************************************************************/

// The synopsys directives "translate_off/translate_on" specified below are

// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis

// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file prog_mem.v when simulating

// the core, prog_mem. When compiling the wrapper file, be sure to

// reference the XilinxCoreLib Verilog simulation library. For detailed

// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module prog_mem(

        addr,

        clk,

        dout);

input [7 : 0] addr;

input clk;

output [47 : 0] dout;

// synopsys translate_off

      BLKMEMSP_V6_2 #(

                8,      // c_addr_width

                "0",     // c_default_data

                256,    // c_depth

                0,       // c_enable_rlocs

                0,       // c_has_default_data

                0,       // c_has_din

                0,       // c_has_en

                0,       // c_has_limit_data_pitch

                0,       // c_has_nd

                0,       // c_has_rdy

                0,       // c_has_rfd

                0,       // c_has_sinit

                0,       // c_has_we

                18,     // c_limit_data_pitch

                "prog_mem.mif", // c_mem_init_file

                0,       // c_pipe_stages

                0,       // c_reg_inputs

                "0",     // c_sinit_value

                48,     // c_width

                0,       // c_write_mode

                "0",     // c_ybottom_addr

                1,      // c_yclk_is_rising

                1,      // c_yen_is_high

                "hierarchy1",   // c_yhierarchy

                0,       // c_ymake_bmm

                "16kx1",        // c_yprimitive_type

                1,      // c_ysinit_is_high

                "1024", // c_ytop_addr

                0,       // c_yuse_single_primitive

                1,      // c_ywe_is_high

                1)      // c_yydisable_warnings

        inst (

                .ADDR(addr),

                .CLK(clk),

                .DOUT(dout),

                .DIN(),

                .EN(),

                .ND(),

                .RFD(),

                .RDY(),

                .SINIT(),

                .WE());

// synopsys translate_on

// FPGA Express black box declaration

// synopsys attribute fpga_dont_touch "true"

// synthesis attribute fpga_dont_touch of prog_mem is "true"

// XST black box declaration

// box_type "black_box"

// synthesis attribute box_type of prog_mem is "black_box"

endmodule