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[/] [brisc/] [trunk/] [reg_file.v] - Diff between revs 2 and 3
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module reg_file (Read_Addr_1, Data_Out_1, Clock);
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parameter aw = 8; //address bus width
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parameter dw = 48; //size of each memory element
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parameter size = (1<<aw);
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output [dw-1:0] Data_Out_1;
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input [aw-1:0] Read_Addr_1;
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input Clock;
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reg [dw-1:0] Reg_File [0:size-1];
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/*
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always @ (posedge Clock) begin
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Data_Out_1 <= Reg_File[Read_Addr_1];
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end
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*/
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//assign Data_Out_a = {{dw-aw{1'b0}}, Read_Addr_1};
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endmodule
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