URL
https://opencores.org/ocsvn/brsfmnce/brsfmnce/trunk
[/] [brsfmnce/] [trunk/] [RTL/] [BRSFmnCE.v] - Diff between revs 2 and 3
Show entire file |
Details |
Blame |
View Log
Rev 2 |
Rev 3 |
Line 39... |
Line 39... |
// memory contents unless Reset also causes reload of the configuration
|
// memory contents unless Reset also causes reload of the configuration
|
// image of the SRAM-based FPGA.
|
// image of the SRAM-based FPGA.
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
module BRSFmnCE (
|
module BRSFmnCE #(
|
parameter pAddr = 10, // Number of Address Bits
|
parameter pAddr = 10, // Number of Address Bits
|
parameter pWidth = 8, // Number of Data Bits
|
parameter pWidth = 8, // Number of Data Bits
|
parameter pRAMInitSize = 128, // Amount Data to Init into FIFO RAM
|
parameter pRAMInitSize = 128, // Amount Data to Init into FIFO RAM
|
parameter pFRAM_Init = "RAMINIT.mif" // RAM Memory Initialization File
|
parameter pFRAM_Init = "RAMINIT.mif" // RAM Memory Initialization File
|
)(
|
)(
|
Line 219... |
Line 219... |
//
|
//
|
// FIFO Block RAM
|
// FIFO Block RAM
|
//
|
//
|
|
|
initial
|
initial
|
$readmemh(pFRAM_Init, FRAM);
|
$readmemh(pFRAM_Init, FRAM, 0, ((1 << pAddr) - 1));
|
|
|
always @(posedge Clk)
|
always @(posedge Clk)
|
begin
|
begin
|
if(Wr)
|
if(Wr)
|
FRAM[WPtr] <= #1 DI;
|
FRAM[WPtr] <= #1 DI;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.