| Line 115... |
Line 115... |
signal oFoundNonce_p : STD_LOGIC := '0';
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signal oFoundNonce_p : STD_LOGIC := '0';
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signal ovNonce : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ovNonce : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ovDigest : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal ovDigest : tDwordArray(0 to 7) := (others=>(others=>'0'));
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-- Add your code here ...
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-- Add your code here ...
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constant cREG_CLK_PERIOD : time := 30 ns; -- 33M Register Clock
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constant cREG_CLK_PERIOD : time := 10 ns; -- 100M Register Clock
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constant cPROC_CLK_PERIOD : time := 10 ns; -- 100M Processing Clock
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constant cPROC_CLK_PERIOD : time := 5 ns; -- 200M Processing Clock
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constant cRESET_INTERVAL : time := 71 ns;
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constant cRESET_INTERVAL : time := 71 ns;
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constant cSTRAT_TEST : integer := 25;
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constant cSTRAT_TEST : integer := 25;
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constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
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constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
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constant cCMD_NOP : std_logic_vector(15 downto 0) := X"0000";
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constant cCMD_NOP : std_logic_vector(15 downto 0) := X"0000";
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| Line 208... |
Line 208... |
elsif rising_edge(iClkReg) then
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elsif rising_edge(iClkReg) then
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if sMidStateValid = '1' then
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if sMidStateValid = '1' then
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svWriteCnt <= svWriteCnt + '1';
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svWriteCnt <= svWriteCnt + '1';
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end if;
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end if;
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if svWriteCnt(3 downto 0) = X"F" and svWriteCnt(15 downto 4) <= conv_std_logic_vector(13, 12) then
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if svWriteCnt(1 downto 0) = "11" and svWriteCnt(13 downto 2) <= conv_std_logic_vector(13, 12) then
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iValid_p <= '1';
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iValid_p <= '1';
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else
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else
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iValid_p <= '0';
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iValid_p <= '0';
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end if;
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end if;
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end if;
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end if;
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| Line 222... |
Line 222... |
begin
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begin
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if iRst_async = '1' then
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if iRst_async = '1' then
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ivAddr <= (others=>'0');
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ivAddr <= (others=>'0');
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ivData <= (others=>'0');
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ivData <= (others=>'0');
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elsif rising_edge(iClkReg) then
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elsif rising_edge(iClkReg) then
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if svWriteCnt(3 downto 0) = X"F" then
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if svWriteCnt(1 downto 0) = "11" then
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case svWriteCnt(15 downto 4) is
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case svWriteCnt(13 downto 2) is
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when X"000" =>
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when X"000" =>
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ivAddr <= X"0";
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ivAddr <= X"0";
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ivData <= svMidState(0);
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ivData <= svMidState(0);
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when X"001" =>
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when X"001" =>
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| Line 270... |
Line 270... |
ivAddr <= X"A";
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ivAddr <= X"A";
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ivData <= svWork(18);
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ivData <= svWork(18);
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when X"00B" =>
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when X"00B" =>
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ivAddr <= X"B";
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ivAddr <= X"B";
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ivData <= svWork(19) - X"20";
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ivData <= svWork(19) - X"02";
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when X"00C" =>
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when X"00C" =>
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ivAddr <= X"C";
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ivAddr <= X"C";
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ivData <= svWork(19) + X"20";
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ivData <= svWork(19) + X"02";
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when X"00D" =>
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when X"00D" =>
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ivAddr <= cCMD_ADDR;
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ivAddr <= cCMD_ADDR;
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ivData <= X"0000" & cCMD_START;
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ivData <= X"0000" & cCMD_START;
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