URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
[/] [bustap-jtag/] [trunk/] [doc/] [Revision History.txt] - Diff between revs 6 and 18
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 6 |
Rev 18 |
Line 3... |
Line 3... |
|
|
2.0 Code base for 2.x development. Added pipelined bus access capture support.
|
2.0 Code base for 2.x development. Added pipelined bus access capture support.
|
|
|
2.1 Added new features: 1. Multiple address filter selection; 2. Read access capture support; 3. Full trigger condition support; 4. Updated GUI; 5. Updated wrapper example with glitch filter and stable address/data capture.
|
2.1 Added new features: 1. Multiple address filter selection; 2. Read access capture support; 3. Full trigger condition support; 4. Updated GUI; 5. Updated wrapper example with glitch filter and stable address/data capture.
|
|
|
|
2.2 Added new features: 1. Multiple capture filter selection in the Tk GUI. 2. Read transaction capture. 3. Adjustable pre-trigger capture. 4. Capture content with transaction timing information.
|
|
|
|
2.3 Added support for Xilinx Devices with Chipscope VIO.
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.