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https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
[/] [bustap-jtag/] [trunk/] [rtl/] [altera/] [virtual_jtag_adda_fifo.v] - Diff between revs 10 and 11
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Rev 11 |
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//**************************************************************
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//**************************************************************
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`include "jtag_sim_define.h"
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`include "jtag_sim_define.h"
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module virtual_jtag_adda_fifo(clk,wr_en,data_in);
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module virtual_jtag_adda_fifo(clk,wr_in,data_in,rd_in);
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parameter data_width = 32,
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parameter data_width = 32,
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fifo_depth = 256,
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fifo_depth = 256,
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addr_width = 8,
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addr_width = 8,
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al_full_val = 255,
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al_full_val = 255,
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al_empt_val = 0;
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al_empt_val = 0;
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input clk;
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input clk;
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input wr_en;
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input wr_in, rd_in;
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input [data_width-1:0] data_in;
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input [data_width-1:0] data_in;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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reg tdo;
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reg tdo;
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reg [addr_width-1:0] usedw_instr_reg;
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reg [addr_width-1:0] usedw_instr_reg;
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wire al_full;
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wire al_full;
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reg read_instr_d1;
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reg read_instr_d1;
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reg read_instr_d2;
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reg read_instr_d2;
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reg read_instr_d3;
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reg read_instr_d3;
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wire rd_en = read_instr_d2 & !read_instr_d3;
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wire rd_en = rd_in | (read_instr_d2 & !read_instr_d3);
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wire wr_en = wr_in;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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read_instr_d1 <= 1'b0;
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read_instr_d1 <= 1'b0;
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