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//**************************************************************
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//**************************************************************
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`include "jtag_sim_define.h"
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`include "jtag_sim_define.h"
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module virtual_jtag_adda_trig(trig_out);
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module virtual_jtag_adda_trig(trig_out, pnum_out);
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parameter trig_width = 32;
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parameter trig_width = 32;
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parameter pnum_width = 10;
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output [trig_width-1:0] trig_out;
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output [trig_width-1:0] trig_out;
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output [pnum_width-1:0] pnum_out;
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reg [trig_width-1:0] trig_out;
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reg [trig_width-1:0] trig_out;
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reg [pnum_width-1:0] pnum_out;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
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reg tdo;
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reg tdo;
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reg [trig_width-1:0] trig_instr_reg;
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reg [trig_width-1:0] trig_instr_reg;
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reg [pnum_width-1:0] pnum_instr_reg;
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reg bypass_reg;
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reg bypass_reg;
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wire [1:0] ir_in;
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wire [1:0] ir_in;
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wire trig_instr = ~ir_in[1] & ir_in[0]; // 1
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wire trig_instr = ~ir_in[1] & ir_in[0]; // 1
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wire pnum_instr = ir_in[1] & ~ir_in[0]; // 2
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always @(posedge tck)
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always @(posedge tck)
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begin
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begin
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if (trig_instr && e1dr)
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if (trig_instr && e1dr)
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trig_out <= trig_instr_reg;
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trig_out <= trig_instr_reg;
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end
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end
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always @(posedge tck)
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begin
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if (pnum_instr && e1dr)
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pnum_out <= pnum_instr_reg;
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end
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/* trig_instr Instruction Handler */
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/* trig_instr Instruction Handler */
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always @ (posedge tck)
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always @ (posedge tck)
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if ( trig_instr && cdr )
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if ( trig_instr && cdr )
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trig_instr_reg <= trig_instr_reg;
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trig_instr_reg <= trig_instr_reg;
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else if ( trig_instr && sdr )
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else if ( trig_instr && sdr )
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trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};
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trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};
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/* pnum_instr Instruction Handler */
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always @ (posedge tck)
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if ( pnum_instr && cdr )
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pnum_instr_reg <= pnum_instr_reg;
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else if ( pnum_instr && sdr )
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pnum_instr_reg <= {tdi, pnum_instr_reg[pnum_width-1:1]};
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/* Bypass register */
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/* Bypass register */
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always @ (posedge tck)
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always @ (posedge tck)
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bypass_reg <= tdi;
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bypass_reg <= tdi;
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/* Node TDO Output */
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/* Node TDO Output */
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always @ ( trig_instr, trig_instr_reg, bypass_reg )
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always @ ( trig_instr, trig_instr_reg, pnum_instr, pnum_instr_reg, bypass_reg )
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begin
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begin
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if (trig_instr)
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if (trig_instr)
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tdo <= trig_instr_reg[0];
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tdo <= trig_instr_reg[0];
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else if (pnum_instr)
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tdo <= pnum_instr_reg[0];
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else
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else
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tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
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tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
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end
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end
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sld_virtual_jtag sld_virtual_jtag_component (
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sld_virtual_jtag sld_virtual_jtag_component (
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