| Line 52... |
Line 52... |
wire [31:0] trig_data = trig_cond[31:0];
|
wire [31:0] trig_data = trig_cond[31:0];
|
reg trig_cond_ok,trig_cond_ok_d1;
|
reg trig_cond_ok,trig_cond_ok_d1;
|
// for capture storage
|
// for capture storage
|
wire [49:0] capture_in;
|
wire [49:0] capture_in;
|
wire capture_wr;
|
wire capture_wr;
|
|
// for pretrigger capture
|
|
wire [9:0] pretrig_num;
|
|
reg [9:0] pretrig_cnt;
|
|
wire pretrig_full;
|
|
wire pretrig_wr;
|
|
reg pretrig_wr_d1,pretrig_rd;
|
|
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
// Capture logic main
|
// Capture logic main
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
|
|
| Line 116... |
Line 122... |
end
|
end
|
// trigger gate kept open until trigger stoped
|
// trigger gate kept open until trigger stoped
|
end
|
end
|
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
|
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
|
|
|
// generate capture wr-in
|
// generate capture wr_in
|
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
|
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
|
assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
|
assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
|
|
|
|
// generate pre-trigger wr_in
|
|
assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
|
|
assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
|
|
always @(posedge clk)
|
|
begin
|
|
if (!trig_en || (trig_en && !trig_set)) begin
|
|
pretrig_cnt <= 10'd0;
|
|
pretrig_wr_d1<= 1'b0;
|
|
pretrig_rd <= 1'b0;
|
|
end
|
|
else if (!pretrig_full) begin
|
|
pretrig_cnt <= pretrig_cnt + addr_mask_ok;
|
|
pretrig_wr_d1<= 1'b0;
|
|
pretrig_rd <= 1'b0;
|
|
end
|
|
else if (pretrig_full) begin
|
|
pretrig_cnt <= pretrig_cnt;
|
|
pretrig_wr_d1<= pretrig_wr;
|
|
pretrig_rd <= pretrig_wr_d1;
|
|
end
|
|
end
|
|
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
// Instantiate vendor specific JTAG functions
|
// Instantiate vendor specific JTAG functions
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
|
|
// index 0, instantiate capture fifo, as output
|
// index 0, instantiate capture fifo, as output
|
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
|
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
|
.clk(clk),
|
.clk(clk),
|
.wr_en(capture_wr),
|
.wr_in(capture_wr || pretrig_wr),
|
.data_in(capture_in)
|
.data_in(capture_in),
|
|
.rd_in(pretrig_rd)
|
);
|
);
|
defparam
|
defparam
|
u_virtual_jtag_adda_fifo.data_width = 50,
|
u_virtual_jtag_adda_fifo.data_width = 50,
|
u_virtual_jtag_adda_fifo.fifo_depth = 512,
|
u_virtual_jtag_adda_fifo.fifo_depth = 512,
|
u_virtual_jtag_adda_fifo.addr_width = 9,
|
u_virtual_jtag_adda_fifo.addr_width = 9,
|
| Line 165... |
Line 194... |
u_virtual_jtag_addr_mask.mask_enabl = 4,
|
u_virtual_jtag_addr_mask.mask_enabl = 4,
|
u_virtual_jtag_addr_mask.addr_width = 32;
|
u_virtual_jtag_addr_mask.addr_width = 32;
|
|
|
// index 2, instantiate capture trigger, as input
|
// index 2, instantiate capture trigger, as input
|
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
|
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
|
.trig_out(trig_cond)
|
.trig_out(trig_cond),
|
|
.pnum_out(pretrig_num)
|
);
|
);
|
defparam
|
defparam
|
u_virtual_jtag_adda_trig.trig_width = 56;
|
u_virtual_jtag_adda_trig.trig_width = 56,
|
|
u_virtual_jtag_adda_trig.pnum_width = 10;
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
