| Line 50... |
Line 50... |
wire trig_set = trig_cond[48];
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wire trig_set = trig_cond[48];
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wire [15:0] trig_addr = trig_cond[47:32];
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wire [15:0] trig_addr = trig_cond[47:32];
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wire [31:0] trig_data = trig_cond[31:0];
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wire [31:0] trig_data = trig_cond[31:0];
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reg trig_cond_ok,trig_cond_ok_d1;
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reg trig_cond_ok,trig_cond_ok_d1;
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// for capture storage
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// for capture storage
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wire [49:0] capture_in;
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wire [81:0] capture_in;
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wire capture_wr;
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wire capture_wr;
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// for pretrigger capture
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// for pretrigger capture
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wire [9:0] pretrig_num;
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wire [9:0] pretrig_num;
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reg [9:0] pretrig_cnt;
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reg [9:0] pretrig_cnt;
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wire pretrig_full;
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wire pretrig_full;
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wire pretrig_wr;
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wire pretrig_wr;
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reg pretrig_wr_d1,pretrig_rd;
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reg pretrig_wr_d1,pretrig_rd;
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// for inter capture timer
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reg [31:0] inter_cap_cnt;
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|
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// Capture logic main
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// Capture logic main
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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|
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| Line 123... |
Line 125... |
// trigger gate kept open until trigger stoped
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// trigger gate kept open until trigger stoped
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end
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end
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wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
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wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
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|
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// generate capture wr_in
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// generate capture wr_in
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assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
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assign capture_in = {trig_cond_ok_pulse,wr_en_d1,inter_cap_cnt,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
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assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
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assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
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|
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// generate pre-trigger wr_in
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// generate pre-trigger wr_in
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assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
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assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
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assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
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assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
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| Line 148... |
Line 150... |
pretrig_wr_d1<= pretrig_wr;
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pretrig_wr_d1<= pretrig_wr;
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pretrig_rd <= pretrig_wr_d1;
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pretrig_rd <= pretrig_wr_d1;
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end
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end
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end
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end
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|
|
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// generate interval counter
|
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always @(posedge clk)
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|
begin
|
|
if (capture_wr || pretrig_wr)
|
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inter_cap_cnt <= 32'd0;
|
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else if (inter_cap_cnt[31])
|
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inter_cap_cnt <= 32'd3000000000;
|
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else
|
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inter_cap_cnt <= inter_cap_cnt + 32'd1;
|
|
end
|
|
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// Instantiate vendor specific JTAG functions
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// Instantiate vendor specific JTAG functions
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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|
|
// index 0, instantiate capture fifo, as output
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// index 0, instantiate capture fifo, as output
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| Line 160... |
Line 173... |
.wr_in(capture_wr || pretrig_wr),
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.wr_in(capture_wr || pretrig_wr),
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.data_in(capture_in),
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.data_in(capture_in),
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.rd_in(pretrig_rd)
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.rd_in(pretrig_rd)
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);
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);
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defparam
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defparam
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u_virtual_jtag_adda_fifo.data_width = 50,
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u_virtual_jtag_adda_fifo.data_width = 82,
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u_virtual_jtag_adda_fifo.fifo_depth = 512,
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u_virtual_jtag_adda_fifo.fifo_depth = 512,
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u_virtual_jtag_adda_fifo.addr_width = 9,
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u_virtual_jtag_adda_fifo.addr_width = 9,
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u_virtual_jtag_adda_fifo.al_full_val = 511,
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u_virtual_jtag_adda_fifo.al_full_val = 511,
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u_virtual_jtag_adda_fifo.al_empt_val = 0;
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u_virtual_jtag_adda_fifo.al_empt_val = 0;
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|
|
