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https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
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##############################################################
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##############################################################
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#
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#
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# Xilinx Core Generator version 14.2
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# Xilinx Core Generator version 14.3
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# Date: Tue Nov 20 02:34:08 2012
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# Date: Fri Feb 07 09:32:54 2014
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#
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#
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##############################################################
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##############################################################
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#
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#
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# This file contains the customisation parameters for a
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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CSET enable_asynchronous_output_port=false
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CSET enable_asynchronous_output_port=false
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CSET enable_synchronous_input_port=true
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CSET enable_synchronous_input_port=true
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CSET enable_synchronous_output_port=true
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CSET enable_synchronous_output_port=true
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CSET example_design=true
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CSET example_design=true
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CSET invert_clock_input=false
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CSET invert_clock_input=false
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CSET synchronous_input_port_width=92
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CSET synchronous_input_port_width=108
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CSET synchronous_output_port_width=2
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CSET synchronous_output_port_width=2
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# END Parameters
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# END Parameters
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# BEGIN Extra information
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# BEGIN Extra information
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MISC pkg_timestamp=2012-07-21T03:12:17Z
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MISC pkg_timestamp=2012-10-12T23:08:55Z
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# END Extra information
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# END Extra information
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GENERATE
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GENERATE
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# CRC: 9f8da0d5
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# CRC: 4363574a
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# CRC: 4363574a
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# CRC: 4363574a
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