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URL https://opencores.org/ocsvn/bw_tiff_compression/bw_tiff_compression/trunk

Subversion Repositories bw_tiff_compression

[/] [bw_tiff_compression/] [trunk/] [capture_manager.vhd] - Diff between revs 2 and 8

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Line 22... Line 22...
 
 
                MAX_CODE_LEN_G                  : integer := 28;
                MAX_CODE_LEN_G                  : integer := 28;
                MAX_CODE_LEN_WIDTH_G            : integer := 5;
                MAX_CODE_LEN_WIDTH_G            : integer := 5;
                SEG_OUTPUT_WIDTH_G              : integer := 8;
                SEG_OUTPUT_WIDTH_G              : integer := 8;
 
 
                TX_MEMORY_SIZE_G                : integer := 4;
                TX_MEMORY_SIZE_G                : integer := 4000;
                TX_MEMORY_ADDRESS_WIDTH_G       : integer := 12;
                TX_MEMORY_ADDRESS_WIDTH_G       : integer := 12;
                TX_MEMORY_WIDTH_G               : integer := 8;
                TX_MEMORY_WIDTH_G               : integer := 8;
 
 
                --@26.6MHz
                --@26.6MHz
                BAUD_DIVIDE_G                   : integer := 15;        --115200 baud
                BAUD_DIVIDE_G                   : integer := 15;        --115200 baud
Line 53... Line 53...
                led0_o  : out STD_LOGIC;
                led0_o  : out STD_LOGIC;
                led1_o  : out STD_LOGIC;
                led1_o  : out STD_LOGIC;
                led2_o  : out STD_LOGIC;
                led2_o  : out STD_LOGIC;
                led3_o  : out STD_LOGIC;
                led3_o  : out STD_LOGIC;
 
 
                sw_i : in STD_LOGIC_VECTOR(6 downto 0)
                sw_i : in STD_LOGIC_VECTOR(6 downto 0);
 
 
 
                --Testbench connections
 
                CCITT4_run_len_code_o       : out STD_LOGIC_VECTOR (MAX_CODE_LEN_G-1 downto 0);
 
                CCITT4_run_len_code_width_o : out STD_LOGIC_VECTOR (MAX_CODE_LEN_WIDTH_G-1 downto 0);
 
                CCITT4_run_len_code_valid_o : out STD_LOGIC;
 
                CCITT4_frame_finished_o     : out STD_LOGIC
        );
        );
end capture_manager;
end capture_manager;
 
 
architecture Behavioral of capture_manager is
architecture Behavioral of capture_manager is
        type state_type is (S_Start, S_WaitForChar, S_WaitForNewFrame, S_CaptureStoreFrame,
        type state_type is (S_Start, S_WaitForChar, S_WaitForNewFrame, S_CaptureStoreFrame,
Line 125... Line 131...
 
 
                --Other signals
                --Other signals
        signal fsync_prev                    : STD_LOGIC             := '0';
        signal fsync_prev                    : STD_LOGIC             := '0';
        signal tx_mem_overflow               : std_logic             := '0';
        signal tx_mem_overflow               : std_logic             := '0';
 
 
        component CCITT4_v2
 
                port(
 
                        pclk_i               : in  STD_LOGIC;
 
                        fsync_i              : in  STD_LOGIC;
 
                        rsync_i              : in  STD_LOGIC;
 
                        pix_i                : in  STD_LOGIC;
 
                        run_len_code_o       : out STD_LOGIC_VECTOR(MAX_CODE_LEN_G - 1 downto 0);
 
                        run_len_code_width_o : out STD_LOGIC_VECTOR(MAX_CODE_LEN_WIDTH_G - 1 downto 0);
 
                        run_len_code_valid_o : out STD_LOGIC;
 
                        frame_finished_o     : out STD_LOGIC;
 
                        fax4_x               : buffer unsigned(COL_INDEX_WIDTH_G - 1 downto 0) := (others => '0');
 
                        fax4_y               : buffer unsigned(ROW_INDEX_WIDTH_G - 1 downto 0) := (others => '0')
 
                );
 
        end component CCITT4_v2;
 
 
 
begin
begin
        CCITT4_ins : CCITT4_v2
        CCITT4_ins : entity work.CCITT4_v2
        Port Map(
        Port Map(
                pclk_i    => pclk_i,
                pclk_i    => pclk_i,
                fsync_i  => fsync_i,
                fsync_i  => fsync_i,
                rsync_i  => rsync_i,
                rsync_i  => rsync_i,
                pix_i  => pix,
                pix_i  => pix,
                run_len_code_o  => run_len_code_CCITT4,
                run_len_code_o  => run_len_code_CCITT4,
                run_len_code_width_o  => run_len_code_width_CCITT4,
                run_len_code_width_o  => run_len_code_width_CCITT4,
                run_len_code_valid_o  => run_len_code_valid_CCITT4,
                run_len_code_valid_o  => run_len_code_valid_CCITT4,
                frame_finished_o  => frame_finished_CCITT4,
                frame_finished_o  => frame_finished_CCITT4
                fax4_x => fax4_x,
 
                fax4_y => fax4_y
 
        );
        );
 
 
        byte_segmentation_ins_v5 : entity work.byte_segmentation_v5
        byte_segmentation_ins_v5 : entity work.byte_segmentation_v5
        Generic Map(
        Generic Map(
                INPUT_WIDTH_G =>  MAX_CODE_LEN_G,
                INPUT_WIDTH_G =>  MAX_CODE_LEN_G,
Line 382... Line 371...
        vgaGreen <= pix_data_i(7 downto 5) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7) & pix_data_i(7);
        vgaGreen <= pix_data_i(7 downto 5) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7) & pix_data_i(7);
        vgaBlue <= pix_data_i(7 downto 6) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7);
        vgaBlue <= pix_data_i(7 downto 6) when sw_i(0) = '0' else pix_data_i(7) & pix_data_i(7);
        vga_fsync_o <= fsync_i;
        vga_fsync_o <= fsync_i;
        vga_rsync_o <= rsync_i;
        vga_rsync_o <= rsync_i;
 
 
 
        CCITT4_run_len_code_o <= run_len_code_CCITT4;
 
        CCITT4_run_len_code_width_o <= run_len_code_width_CCITT4;
 
        CCITT4_run_len_code_valid_o <= run_len_code_valid_CCITT4;
 
        CCITT4_frame_finished_o <= frame_finished_CCITT4;
 
 
end Behavioral;
end Behavioral;
 
 
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