?rev1line? |
?rev2line? |
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/*
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* Kernel Entry point for secondary cpus
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*
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* Copyright (C) 2010 B Labs Ltd.
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* Author: Prem Mallappa
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*/
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#include INC_ARCH(asm.h)
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#include INC_PLAT(offsets.h)
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#include INC_ARCH(asm-macros.S)
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#define C15_C0_M 0x0001 /* MMU */
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#define C15_C0_A 0x0002 /* Alignment */
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#define C15_C0_C 0x0004 /* (D) Cache */
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#define C15_C0_W 0x0008 /* Write buffer */
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#define C15_C0_B 0x0080 /* Endianness */
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#define C15_C0_S 0x0100 /* System */
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#define C15_C0_R 0x0200 /* ROM */
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#define C15_C0_Z 0x0800 /* Branch Prediction */
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#define C15_C0_I 0x1000 /* I cache */
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#define C15_C0_V 0x2000 /* High vectors */
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.section .text.head
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BEGIN_PROC(__smp_start)
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msr cpsr_fxsc, #ARM_NOIRQ_SVC
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/* Disable mmu if it is enabled */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #C15_C0_M @ Disable MMU
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bic r0, r0, #C15_C0_C @ Disable (D) Cache
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bic r0, r0, #C15_C0_I @ Disable I cache
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bic r0, r0, #C15_C0_W @ Disable Write buffer
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mcr p15, 0, r0, c1, c0, 0
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/* Setup boot stack (physical address) */
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/*
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* Each processor gets a unique 1024 byte stack.
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* This stack is used until the first task becomes
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* runnable, so there needs to be one for each core
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*
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* +----------+
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* |CPU3 Stack|
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* +----------+
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* |CPU2 Stack|
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* +----------+
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* |CPU1 Stack|
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* +----------+
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* |CPU0 Stack|
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* +----------+ _bootstack_physical
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*/
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get_cpuid r0
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mov r0, r0, lsl #12 /* 4 KB stack per-cpu */
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ldr sp, _secondary_cpu_stack
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sub sp, sp, r0
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/*
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* Each processor will get its own irq/fiq/abt/und/svc stack
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* of size 16 bytes per mode. Each mode would have 64 bytes
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* of stack used in total for 4 cores.
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*
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* Note, unlike SVC mode all abort modes also include the
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* stack for primary core, i.e CPU0. There's no separation
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* of primary and secondary stack regions.
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*
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* +------------------+ __abt_stack_high
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* | CPU0 ABT Stack |
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* +------------------+ __abt_stack_high - 0x10
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* | CPU1 ABT Stack |
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* +------------------+ __abt_stack_high - 0x20
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* | CPU2 ABT Stack |
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* +------------------+ __abt_stack_high - 0x30
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* | CPU3 ABT Stack |
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* +------------------+ __abt_stack_high - 0x40
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*
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*/
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get_cpuid r0
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mov r0, r0, lsl #4 /* 16 byte stack for each core */
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/* Exception stacks are defined in vector page */
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msr cpsr_fcx, #ARM_NOIRQ_ABT
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ldr sp, _sec_kern_abt_stack
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sub sp, sp, r0
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msr cpsr_fcx, #ARM_NOIRQ_IRQ
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ldr sp, _sec_kern_irq_stack
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sub sp, sp, r0
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msr cpsr_fcx, #ARM_NOIRQ_FIQ
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ldr sp, _sec_kern_fiq_stack
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sub sp, sp, r0
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msr cpsr_fcx, #ARM_NOIRQ_UND
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ldr sp, _sec_kern_und_stack
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sub sp, sp, r0
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msr cpsr_fcx, #ARM_NOIRQ_SVC
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/* Jump to start_kernel */
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bl smp_secondary_init
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/* Never reached */
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1:
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b 1b
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_secondary_cpu_stack:
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.word _bootstack_physical
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/* Exception stacks are defined in vector page */
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_sec_kern_abt_stack:
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.word __abt_stack_high
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_sec_kern_irq_stack:
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.word __irq_stack_high
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_sec_kern_fiq_stack:
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.word __fiq_stack_high
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_sec_kern_und_stack:
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.word __und_stack_high
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