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/*
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* ARM Kernel entry point
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#include INC_ARCH(asm.h)
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#define C15_C0_M 0x0001 /* MMU */
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#define C15_C0_A 0x0002 /* Alignment */
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#define C15_C0_C 0x0004 /* (D) Cache */
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#define C15_C0_W 0x0008 /* Write buffer */
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#define C15_C0_B 0x0080 /* Endianness */
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#define C15_C0_S 0x0100 /* System */
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#define C15_C0_R 0x0200 /* ROM */
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#define C15_C0_Z 0x0800 /* Branch Prediction */
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#define C15_C0_I 0x1000 /* I cache */
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#define C15_C0_V 0x2000 /* High vectors */
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/*
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* This is the entry point of the L4 ARM architecture.
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* The boot loader must call _start with the processor in privileged
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* mode and mmu disabled.
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*/
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.section .text.head
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BEGIN_PROC(_start)
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/* Setup status register for supervisor mode, interrupts disabled */
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msr cpsr_fcxs, #ARM_MODE_SVC
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/* Disable mmu if it is enabled */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #C15_C0_M @ Disable MMU
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bic r0, r0, #C15_C0_C @ Disable (D) Cache
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bic r0, r0, #C15_C0_I @ Disable I cache
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bic r0, r0, #C15_C0_W @ Disable Write buffer
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bic r0, r0, #C15_C0_Z @ Disable Branch prediction
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mcr p15, 0, r0, c1, c0, 0
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/* Setup boot stack (physical address) */
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ldr sp, _kernel_init_stack
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/* Exception stacks are defined in vector page */
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msr cpsr_fc, #ARM_NOIRQ_ABT
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ldr sp, _kernel_abt_stack
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msr cpsr_fc, #ARM_NOIRQ_IRQ
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ldr sp, _kernel_irq_stack
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msr cpsr_fc, #ARM_NOIRQ_FIQ
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ldr sp, _kernel_fiq_stack
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msr cpsr_fc, #ARM_NOIRQ_UND
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ldr sp, _kernel_und_stack
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msr cpsr_fc, #ARM_NOIRQ_SVC
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/* Jump to start_kernel */
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bl start_kernel
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/* Never reached */
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1:
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b 1b
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_kernel_init_stack:
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.word _bootstack_physical
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/* Exception stacks are defined in vector page */
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_kernel_abt_stack:
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.word __abt_stack_high
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_kernel_irq_stack:
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.word __irq_stack_high
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_kernel_fiq_stack:
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.word __fiq_stack_high
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_kernel_und_stack:
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.word __und_stack_high
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