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[/] [c16/] [trunk/] [vhdl/] [BaudGen.vhd] - Diff between revs 2 and 9
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Rev 9 |
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Line 11... |
--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity BaudGen is
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entity BaudGen is
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Generic(bg_clock_freq : integer; bg_baud_rate : integer);
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Generic(bg_clock_freq : integer; bg_baud_rate : integer);
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Port( CLK_I : in std_logic;
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Port( CLK_I : in std_logic;
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CLR : in std_logic;
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RST_I : in std_logic;
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CE_16 : out std_logic
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CE_16 : out std_logic
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);
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);
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end BaudGen;
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end BaudGen;
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architecture Behavioral of BaudGen is
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architecture Behavioral of BaudGen is
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process(CLK_I)
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process(CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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CE_16 <= '0'; -- make CE_16 stay on for (at most) one cycle
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CE_16 <= '0'; -- make CE_16 stay on for (at most) one cycle
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if (CLR = '1') then
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if (RST_I = '1') then
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COUNTER <= 0;
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COUNTER <= 0;
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elsif (COUNTER >= limit) then
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elsif (COUNTER >= limit) then
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CE_16 <= '1';
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CE_16 <= '1';
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COUNTER <= COUNTER - limit;
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COUNTER <= COUNTER - limit;
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else
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else
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