| Line 5... |
Line 5... |
use work.cpu_pack.ALL;
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use work.cpu_pack.ALL;
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library UNISIM;
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library UNISIM;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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entity cpu16 is
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entity cpu is
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PORT( CLK_I : in STD_LOGIC;
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PORT( CLK_I : in STD_LOGIC;
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T2 : out STD_LOGIC;
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SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
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SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
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SER_IN : in STD_LOGIC;
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SER_IN : in STD_LOGIC;
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SER_OUT : out STD_LOGIC;
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SER_OUT : out STD_LOGIC;
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| Line 28... |
Line 27... |
XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
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XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
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XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
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XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
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XM_WE : out STD_LOGIC;
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XM_WE : out STD_LOGIC;
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XM_CE : out STD_LOGIC
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XM_CE : out STD_LOGIC
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);
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);
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end cpu16;
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end cpu;
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architecture behavioral of cpu16 is
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architecture behavioral of cpu is
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COMPONENT bin_to_7segment
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COMPONENT bin_to_7segment
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PORT( CLK_I : IN std_logic;
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PORT( CLK_I : IN std_logic;
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T2 : IN std_logic;
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PC : IN std_logic_vector(15 downto 0);
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PC : IN std_logic_vector(15 downto 0);
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SEG1 : OUT std_logic_vector(7 downto 1);
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SEG1 : OUT std_logic_vector(7 downto 1);
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SEG2 : OUT std_logic_vector(7 downto 0)
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SEG2 : OUT std_logic_vector(7 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT cpu_engine
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COMPONENT cpu_engine
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PORT( CLK_I : in std_logic;
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PORT( CLK_I : in std_logic;
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T2 : out std_logic;
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DAT_I : in std_logic_vector( 7 downto 0);
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CLR : in std_logic;
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DAT_O : out std_logic_vector( 7 downto 0);
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RST_I : in std_logic;
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ACK_I : in std_logic;
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ADR_O : out std_logic_vector(15 downto 0);
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CYC_O : out std_logic;
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STB_O : out std_logic;
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TGA_O : out std_logic_vector(0 downto 0);
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WE_O : out std_logic;
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INT : in std_logic;
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HALT : out std_logic;
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-- debug signals
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--
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Q_PC : out std_logic_vector(15 downto 0);
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Q_PC : out std_logic_vector(15 downto 0);
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Q_OPC : out std_logic_vector( 7 downto 0);
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Q_OPC : out std_logic_vector( 7 downto 0);
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Q_CAT : out op_category;
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Q_CAT : out op_category;
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Q_IMM : out std_logic_vector(15 downto 0);
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Q_IMM : out std_logic_vector(15 downto 0);
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Q_CYC : out cycle;
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Q_CYC : out cycle;
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-- input/output
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INT : in std_logic;
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IO_ADR : out std_logic_vector(7 downto 0);
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IO_RD : out std_logic;
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IO_WR : out std_logic;
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IO_RDAT : in std_logic_vector( 7 downto 0);
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-- memory
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XM_ADR : out std_logic_vector(15 downto 0);
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XM_RDAT : in std_logic_vector( 7 downto 0);
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XM_WDAT : out std_logic_vector( 7 downto 0);
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XM_WE : out std_logic;
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XM_CE : out std_logic;
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-- select signals
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-- select signals
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Q_SX : out std_logic_vector(1 downto 0);
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Q_SX : out std_logic_vector(1 downto 0);
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Q_SY : out std_logic_vector(3 downto 0);
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Q_SY : out std_logic_vector(3 downto 0);
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Q_OP : out std_logic_vector(4 downto 0);
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Q_OP : out std_logic_vector(4 downto 0);
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Q_SA : out std_logic_vector(4 downto 0);
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Q_SA : out std_logic_vector(4 downto 0);
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| Line 79... |
Line 76... |
Q_WE_LL : out std_logic;
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Q_WE_LL : out std_logic;
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Q_WE_SP : out SP_OP;
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Q_WE_SP : out SP_OP;
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Q_RR : out std_logic_vector(15 downto 0);
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Q_RR : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_SP : out std_logic_vector(15 downto 0);
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Q_SP : out std_logic_vector(15 downto 0)
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HALT : out std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT input_output
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COMPONENT input_output
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PORT( CLK_I : IN std_logic;
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PORT( CLK_I : IN std_logic;
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T2 : IN std_logic;
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CYC_I : IN std_logic;
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CLR : OUT std_logic;
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RST_O : OUT std_logic;
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STB_I : IN std_logic;
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ACK_O : OUT std_logic;
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IO : IN std_logic;
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WE_I : IN std_logic;
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ADR_I : IN std_logic_vector(7 downto 0);
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TEMP_SPO : IN std_logic;
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TEMP_SPO : IN std_logic;
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TEMP_SPI : OUT std_logic;
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TEMP_SPI : OUT std_logic;
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TEMP_CE : OUT std_logic;
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TEMP_CE : OUT std_logic;
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TEMP_SCLK : OUT std_logic;
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TEMP_SCLK : OUT std_logic;
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| Line 100... |
Line 101... |
SER_OUT : OUT std_logic;
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SER_OUT : OUT std_logic;
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SWITCH : IN std_logic_vector(9 downto 0);
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SWITCH : IN std_logic_vector(9 downto 0);
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LED : OUT std_logic_vector(7 downto 0);
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LED : OUT std_logic_vector(7 downto 0);
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IO_RD : IN std_logic;
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IO_WR : IN std_logic;
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IO_ADR : IN std_logic_vector(7 downto 0);
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IO_WDAT : IN std_logic_vector(7 downto 0);
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IO_WDAT : IN std_logic_vector(7 downto 0);
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IO_RDAT : OUT std_logic_vector(7 downto 0);
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IO_RDAT : OUT std_logic_vector(7 downto 0);
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INT : OUT std_logic;
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INT : OUT std_logic;
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HALT : in std_logic
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HALT : in std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal CLR : std_logic;
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signal CLR : std_logic;
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signal LT2 : std_logic;
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signal ADR : std_logic_vector(15 downto 0);
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signal ADR : std_logic_vector(15 downto 0);
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signal CYC : std_logic;
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signal STB : std_logic;
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signal XM_STB : std_logic;
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signal IO_STB : std_logic;
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signal ACK : std_logic;
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signal XM_ACK : std_logic;
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signal IO_ACK : std_logic;
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signal HALT : std_logic;
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signal HALT : std_logic;
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signal INT : std_logic;
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signal INT : std_logic;
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signal IO_RD : std_logic;
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signal IO : std_logic;
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signal IO_WR : std_logic;
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signal WE : std_logic;
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signal IO_ADR : std_logic_vector( 7 downto 0);
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signal IO_RDAT : std_logic_vector( 7 downto 0);
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signal IO_RDAT : std_logic_vector( 7 downto 0);
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signal IOM_WDAT : std_logic_vector( 7 downto 0);
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signal WDAT : std_logic_vector( 7 downto 0);
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signal PC : std_logic_vector(15 downto 0);
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signal RDAT : std_logic_vector( 7 downto 0);
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signal PC : std_logic_vector(15 downto 0);
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signal Q_C_SX : std_logic_vector(1 downto 0);
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signal Q_C_SX : std_logic_vector(1 downto 0);
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signal Q_C_SY : std_logic_vector(3 downto 0);
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signal Q_C_SY : std_logic_vector(3 downto 0);
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signal Q_C_OP : std_logic_vector(4 downto 0);
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signal Q_C_OP : std_logic_vector(4 downto 0);
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signal Q_C_SA : std_logic_vector(4 downto 0);
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signal Q_C_SA : std_logic_vector(4 downto 0);
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signal Q_C_SMQ : std_logic;
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signal Q_C_SMQ : std_logic;
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| Line 145... |
Line 149... |
signal Q_C_IMM : std_logic_vector(15 downto 0);
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signal Q_C_IMM : std_logic_vector(15 downto 0);
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signal Q_C_CYC : cycle;
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signal Q_C_CYC : cycle;
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begin
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begin
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T2 <= LT2;
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SEG1(0) <= HALT;
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SEG1(0) <= HALT;
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XM_ADR <= ADR;
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XM_ADR <= ADR;
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XM_WDAT <= IOM_WDAT;
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XM_WDAT <= WDAT;
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XM_WE <= WE;
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XM_STB <= STB and not IO;
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IO_STB <= STB and IO;
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XM_ACK <= XM_STB;
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XM_CE <= CYC and not IO;
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RDAT <= IO_RDAT when (IO = '1') else XM_RDAT;
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ACK <= IO_ACK when (IO = '1') else XM_ACK;
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seg7: bin_to_7segment
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seg7: bin_to_7segment
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => LT2,
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PC => PC,
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PC => PC,
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SEG1 => SEG1(7 downto 1),
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SEG1 => SEG1(7 downto 1), -- SEG1(0) is HALT
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SEG2 => SEG2
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SEG2 => SEG2
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);
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);
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eng: cpu_engine
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eng: cpu_engine
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => LT2,
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DAT_I => RDAT,
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CLR => CLR, -- SW-1 (RESET)
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DAT_O => WDAT,
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RST_I => CLR, -- SW-1 (RESET)
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ACK_I => ACK,
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CYC_O => CYC,
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STB_O => STB,
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ADR_O => ADR,
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TGA_O(0) => IO,
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WE_O => WE,
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INT => INT,
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HALT => HALT,
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Q_PC => PC,
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Q_PC => PC,
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Q_OPC => Q_C_OPC,
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Q_OPC => Q_C_OPC,
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Q_CAT => Q_C_CAT,
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Q_CAT => Q_C_CAT,
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Q_IMM => Q_C_IMM,
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Q_IMM => Q_C_IMM,
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Q_CYC => Q_C_CYC,
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Q_CYC => Q_C_CYC,
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INT => INT,
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IO_ADR => IO_ADR,
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IO_RD => IO_RD,
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IO_WR => IO_WR,
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IO_RDAT => IO_RDAT,
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XM_ADR => ADR,
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XM_RDAT => XM_RDAT,
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XM_WDAT => IOM_WDAT,
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XM_WE => XM_WE,
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XM_CE => XM_CE,
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Q_SX => Q_C_SX,
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Q_SX => Q_C_SX,
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Q_SY => Q_C_SY,
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Q_SY => Q_C_SY,
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Q_OP => Q_C_OP,
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Q_OP => Q_C_OP,
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Q_SA => Q_C_SA,
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Q_SA => Q_C_SA,
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Q_SMQ => Q_C_SMQ,
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Q_SMQ => Q_C_SMQ,
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| Line 192... |
Line 200... |
Q_WE_LL => Q_C_WE_LL,
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Q_WE_LL => Q_C_WE_LL,
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Q_WE_SP => Q_C_WE_SP,
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Q_WE_SP => Q_C_WE_SP,
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Q_RR => Q_C_RR,
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Q_RR => Q_C_RR,
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Q_LL => Q_C_LL,
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Q_LL => Q_C_LL,
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Q_SP => Q_C_SP,
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Q_SP => Q_C_SP
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HALT => HALT
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);
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);
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io: input_output
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ino: input_output
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => LT2,
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CYC_I => CYC,
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CLR => CLR,
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RST_O => CLR,
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STB_I => IO_STB,
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ACK_O => IO_ACK,
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TEMP_SPO => TEMP_SPO,
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TEMP_SPO => TEMP_SPO,
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TEMP_SPI => TEMP_SPI,
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TEMP_SPI => TEMP_SPI,
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TEMP_CE => TEMP_CE,
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TEMP_CE => TEMP_CE,
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TEMP_SCLK => TEMP_SCLK,
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TEMP_SCLK => TEMP_SCLK,
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| Line 212... |
Line 221... |
SER_OUT => SER_OUT,
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SER_OUT => SER_OUT,
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SWITCH => SWITCH,
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SWITCH => SWITCH,
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LED => LED,
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LED => LED,
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IO_RD => IO_RD,
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IO => IO,
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IO_WR => IO_WR,
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WE_I => WE,
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IO_ADR => IO_ADR,
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ADR_I => ADR(7 downto 0),
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IO_RDAT => IO_RDAT,
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IO_RDAT => IO_RDAT,
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IO_WDAT => IOM_WDAT,
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IO_WDAT => WDAT,
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INT => INT,
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INT => INT,
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HALT => HALT
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HALT => HALT
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);
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);
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end behavioral;
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end behavioral;
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