URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] [c16/] [trunk/] [vhdl/] [cpu16.npl] - Diff between revs 2 and 7

Rev 2	Rev 7
Line 56...	Line 56...
`[Normal]`	`[Normal]`
`p_ModelSimSignalWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False`	`p_ModelSimSignalWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False`
`p_ModelSimStructWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False`	`p_ModelSimStructWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False`
`_SynthExtractROM=xstvhd, virtexe, Schematic.t_synthesize, 1064066560, False`	`_SynthExtractROM=xstvhd, virtexe, Schematic.t_synthesize, 1064066560, False`
`[STATUS-ALL]`	`[STATUS-ALL]`
`board_cpu.ngcFile=WARNINGS,1064942956`	`board_cpu.ncdFile=WARNINGS,1065278577`
	`board_cpu.ngcFile=WARNINGS,1065278577`
`[STRATEGY-LIST]`	`[STRATEGY-LIST]`
`Normal=True`	`Normal=True`