| Line 205... |
Line 205... |
signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
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signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
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signal C_RR : std_logic_vector(15 downto 0);
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signal C_RR : std_logic_vector(15 downto 0);
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signal RRZ : std_logic;
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signal RRZ : std_logic;
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signal OC_JD : std_logic_vector(15 downto 0);
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signal OC_JD : std_logic_vector(15 downto 0);
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signal C_MQ : std_logic_vector(7 downto 0);
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-- select signals
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-- select signals
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signal C_SX : std_logic_vector(1 downto 0);
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signal C_SX : std_logic_vector(1 downto 0);
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signal C_SY : std_logic_vector(3 downto 0);
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signal C_SY : std_logic_vector(3 downto 0);
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signal C_OP : std_logic_vector(4 downto 0);
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signal C_OP : std_logic_vector(4 downto 0);
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| Line 364... |
Line 363... |
else T2 <= not T2;
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else T2 <= not T2;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(T2, M_PC, ADR, C_IO)
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process(T2, M_PC, ADR, C_IO, C_RD_O, C_WE_O)
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begin
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begin
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if (T2 = '0') then -- opcode fetch
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if (T2 = '0') then -- opcode fetch
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EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
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EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
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-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
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-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
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-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
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-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
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| Line 400... |
Line 399... |
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M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
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M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
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ADR_O <= M_PC when (T2 = '0') else ADR;
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ADR_O <= M_PC when (T2 = '0') else ADR;
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RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
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RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
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process(CLK_I)
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process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
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begin
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begin
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if (rising_edge(CLK_I)) then
|
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if (RST_I = '1') then
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if (RST_I = '1') then
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D_PC <= X"0000";
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D_OPC <= X"01";
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D_CYC <= M1;
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C_PC <= X"0000";
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C_PC <= X"0000";
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C_OPC <= X"01";
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C_OPC <= X"01";
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C_CYC <= M1;
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C_CYC <= M1;
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C_IMM <= X"FFFF";
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C_SX <= "00";
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C_SX <= "00";
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C_SY <= "0000";
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C_SY <= "0000";
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C_OP <= "00000";
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C_OP <= "00000";
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C_SA <= "00000";
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C_SA <= "00000";
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| Line 425... |
Line 419... |
C_WE_SP <= SP_NOP;
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C_WE_SP <= SP_NOP;
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C_IO <= '0';
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C_IO <= '0';
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C_RD_O <= '0';
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C_RD_O <= '0';
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C_WE_O <= '0';
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C_WE_O <= '0';
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LM_WE <= '0';
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LM_WE <= '0';
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elsif (CE = '1' and T2 = '1') then
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elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
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C_CYC <= D_CYC;
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C_CYC <= D_CYC;
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Q_CAT <= D_CAT;
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Q_CAT <= D_CAT;
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C_PC <= D_PC;
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C_PC <= D_PC;
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C_OPC <= D_OPC;
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C_OPC <= D_OPC;
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C_SX <= D_SX;
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C_SX <= D_SX;
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| Line 443... |
Line 437... |
C_IO <= D_IO;
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C_IO <= D_IO;
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C_RD_O <= D_RD_O;
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C_RD_O <= D_RD_O;
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C_WE_O <= D_WE_O;
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C_WE_O <= D_WE_O;
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LM_WE <= D_WE_O and not D_IO;
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LM_WE <= D_WE_O and not D_IO;
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|
|
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end if;
|
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end process;
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|
|
|
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
|
|
begin
|
|
if (RST_I = '1') then
|
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D_PC <= X"0000";
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D_OPC <= X"01";
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D_CYC <= M1;
|
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C_IMM <= X"FFFF";
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|
|
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elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
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if (D_LAST_M = '1') then -- D goes to M1
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if (D_LAST_M = '1') then -- D goes to M1
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-- signals valid for entire opcode...
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-- signals valid for entire opcode... PORTATO FUORI
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D_OPC <= M_OPC;
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D_OPC <= M_OPC;
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D_PC <= M_PC;
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D_PC <= M_PC;
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D_CYC <= M1;
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D_CYC <= M1;
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else
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else
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case D_CYC is
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case D_CYC is
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| Line 460... |
Line 466... |
when M4 => D_CYC <= M5;
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when M4 => D_CYC <= M5;
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when M5 => D_CYC <= M1;
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when M5 => D_CYC <= M1;
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end case;
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end case;
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end if;
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end if;
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end if;
|
end if;
|
end if;
|
|
end process;
|
end process;
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|
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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