| Line 9... |
Line 9... |
--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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use work.cpu_pack.ALL;
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use work.cpu_pack.ALL;
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entity cpu_engine is
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entity cpu_engine is
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PORT( CLK_I : in std_logic;
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PORT( -- WISHBONE interface
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T2 : out std_logic;
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CLK_I : in std_logic;
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CLR : in std_logic;
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DAT_I : in std_logic_vector( 7 downto 0);
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DAT_O : out std_logic_vector( 7 downto 0);
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RST_I : in std_logic;
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ACK_I : in std_logic;
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ADR_O : out std_logic_vector(15 downto 0);
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CYC_O : out std_logic;
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STB_O : out std_logic;
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TGA_O : out std_logic_vector( 0 downto 0); -- '1' if I/O
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WE_O : out std_logic;
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INT : in std_logic;
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HALT : out std_logic;
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-- debug signals
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--
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Q_PC : out std_logic_vector(15 downto 0);
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Q_PC : out std_logic_vector(15 downto 0);
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Q_OPC : out std_logic_vector( 7 downto 0);
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Q_OPC : out std_logic_vector( 7 downto 0);
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Q_CAT : out op_category;
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Q_CAT : out op_category;
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Q_IMM : out std_logic_vector(15 downto 0);
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Q_IMM : out std_logic_vector(15 downto 0);
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Q_CYC : out cycle;
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Q_CYC : out cycle;
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-- input/output
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INT : in std_logic;
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IO_ADR : out std_logic_vector(7 downto 0);
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IO_RD : out std_logic;
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IO_WR : out std_logic;
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IO_RDAT : in std_logic_vector( 7 downto 0);
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-- external memory
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XM_ADR : out std_logic_vector(15 downto 0);
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XM_RDAT : in std_logic_vector( 7 downto 0);
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XM_WDAT : out std_logic_vector( 7 downto 0);
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XM_WE : out std_logic;
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XM_CE : out std_logic;
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-- select signals
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-- select signals
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Q_SX : out std_logic_vector(1 downto 0);
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Q_SX : out std_logic_vector(1 downto 0);
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Q_SY : out std_logic_vector(3 downto 0);
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Q_SY : out std_logic_vector(3 downto 0);
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Q_OP : out std_logic_vector(4 downto 0);
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Q_OP : out std_logic_vector(4 downto 0);
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Q_SA : out std_logic_vector(4 downto 0);
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Q_SA : out std_logic_vector(4 downto 0);
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| Line 46... |
Line 46... |
Q_WE_LL : out std_logic;
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Q_WE_LL : out std_logic;
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Q_WE_SP : out SP_OP;
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Q_WE_SP : out SP_OP;
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Q_RR : out std_logic_vector(15 downto 0);
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Q_RR : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_SP : out std_logic_vector(15 downto 0);
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Q_SP : out std_logic_vector(15 downto 0)
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HALT : out std_logic
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);
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);
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end cpu_engine;
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end cpu_engine;
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architecture Behavioral of cpu_engine is
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architecture Behavioral of cpu_engine is
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-- Unfortunately, the on-chip memory needs a clock to read data.
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-- Therefore we cannot make it wishbone compliant without a speed penalty.
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-- We avoid this problem by making the on-chip memory part of the CPU.
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-- However, as a consequence, you cannot DMA to the on-chip memory.
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--
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-- The on-chip memory is 8K, so that you can run a test SoC without external
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-- memory. For bigger applications, you should use external ROM and RAM and
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-- remove the internal memory entirely (setting EXTERN accordingly).
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--
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COMPONENT memory
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COMPONENT memory
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PORT( CLK_I : IN std_logic;
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PORT( CLK_I : IN std_logic;
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T2 : IN std_logic;
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T2 : IN std_logic;
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CE : IN std_logic;
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CE : IN std_logic;
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PC : IN std_logic_vector(15 downto 0);
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PC : IN std_logic_vector(15 downto 0);
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| Line 102... |
Line 110... |
D_SMQ : out std_logic;
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D_SMQ : out std_logic;
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-- write enable/select signal
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-- write enable/select signal
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D_WE_RR : out std_logic;
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D_WE_RR : out std_logic;
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D_WE_LL : out std_logic;
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D_WE_LL : out std_logic;
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D_WE_M : out std_logic;
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D_WE_SP : out SP_OP;
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D_WE_SP : out SP_OP;
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D_RD_O : out std_logic;
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D_WE_O : out std_logic;
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D_LOCK : out std_logic;
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-- input/output
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-- input/output
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IO_RD : out std_logic;
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D_IO : out std_logic;
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IO_WR : out std_logic;
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PC_OP : out std_logic_vector(2 downto 0);
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PC_OP : out std_logic_vector(2 downto 0);
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LAST_M : out std_logic;
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LAST_M : out std_logic;
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HLT : out std_logic
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HLT : out std_logic
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| Line 136... |
Line 145... |
-- write enable/select signal
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-- write enable/select signal
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WE_RR : in std_logic;
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WE_RR : in std_logic;
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WE_LL : in std_logic;
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WE_LL : in std_logic;
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WE_SP : in SP_OP;
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WE_SP : in SP_OP;
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-- data in signals
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IMM : in std_logic_vector(15 downto 0); -- immediate data
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IMM : in std_logic_vector(15 downto 0); -- immediate data
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M_RDAT : in std_logic_vector( 7 downto 0); -- memory data
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RDAT : in std_logic_vector( 7 downto 0); -- data from memory/IO
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ADR : out std_logic_vector(15 downto 0); -- memory/IO address
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-- memory control signals
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MQ : out std_logic_vector( 7 downto 0); -- data to memory/IO
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ADR : out std_logic_vector(15 downto 0);
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MQ : out std_logic_vector( 7 downto 0);
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-- input/output
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IO_RDAT : in std_logic_vector( 7 downto 0);
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Q_RR : out std_logic_vector(15 downto 0);
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Q_RR : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_SP : out std_logic_vector(15 downto 0)
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Q_SP : out std_logic_vector(15 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- global signals
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-- global signals
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signal CE : std_logic;
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signal CE : std_logic;
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signal LT2 : std_logic;
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signal T2 : std_logic;
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-- memory signals
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-- memory signals
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signal MEM_WDAT : std_logic_vector(7 downto 0);
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signal WDAT : std_logic_vector(7 downto 0);
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signal MEM_RDAT : std_logic_vector(7 downto 0);
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signal RDAT : std_logic_vector(7 downto 0);
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signal M_PC : std_logic_vector(15 downto 0);
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signal M_PC : std_logic_vector(15 downto 0);
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signal M_OPC : std_logic_vector(7 downto 0);
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signal M_OPC : std_logic_vector(7 downto 0);
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-- decoder signals
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-- decoder signals
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--
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--
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| Line 171... |
Line 174... |
signal D_OPC : std_logic_vector(7 downto 0);
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signal D_OPC : std_logic_vector(7 downto 0);
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signal D_CYC : cycle;
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signal D_CYC : cycle;
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signal D_PC : std_logic_vector(15 downto 0); -- debug signal
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signal D_PC : std_logic_vector(15 downto 0); -- debug signal
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signal D_PC_OP : std_logic_vector( 2 downto 0);
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signal D_PC_OP : std_logic_vector( 2 downto 0);
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signal D_LAST_M : std_logic;
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signal D_LAST_M : std_logic;
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signal D_IO_RD : std_logic;
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signal D_IO : std_logic;
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signal D_IO_WR : std_logic;
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-- select signals
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-- select signals
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signal D_SX : std_logic_vector(1 downto 0);
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signal D_SX : std_logic_vector(1 downto 0);
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signal D_SY : std_logic_vector(3 downto 0);
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signal D_SY : std_logic_vector(3 downto 0);
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signal D_OP : std_logic_vector(4 downto 0);
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signal D_OP : std_logic_vector(4 downto 0);
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signal D_SA : std_logic_vector(4 downto 0);
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signal D_SA : std_logic_vector(4 downto 0);
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signal D_SMQ : std_logic;
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signal D_SMQ : std_logic;
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-- write enable/select signals
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-- write enable/select signals
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signal D_WE_RR : std_logic;
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signal D_WE_RR : std_logic;
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signal D_WE_LL : std_logic;
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signal D_WE_LL : std_logic;
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signal D_WE_SP : SP_OP;
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signal D_WE_SP : SP_OP;
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signal D_MEM_WE : std_logic;
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signal D_RD_O : std_logic;
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signal MEM_WE : std_logic;
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signal D_WE_O : std_logic;
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signal D_LOCK : std_logic; -- first cycle
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signal LM_WE : std_logic;
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-- core signals
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-- core signals
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--
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--
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signal C_IMM : std_logic_vector(15 downto 0);
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signal C_IMM : std_logic_vector(15 downto 0);
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signal ADR : std_logic_vector(15 downto 0);
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signal ADR : std_logic_vector(15 downto 0);
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| Line 213... |
Line 220... |
signal C_WE_SP : SP_OP;
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signal C_WE_SP : SP_OP;
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signal XM_OPC : std_logic_vector(7 downto 0);
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signal XM_OPC : std_logic_vector(7 downto 0);
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signal LM_OPC : std_logic_vector(7 downto 0);
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signal LM_OPC : std_logic_vector(7 downto 0);
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signal LM_RDAT : std_logic_vector(7 downto 0);
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signal LM_RDAT : std_logic_vector(7 downto 0);
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signal LXM_RDAT : std_logic_vector(7 downto 0);
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signal XM_RDAT : std_logic_vector(7 downto 0);
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signal OPCS : std_logic;
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signal C_IO : std_logic;
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signal RDATS : std_logic;
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signal C_RD_O : std_logic;
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signal C_WE_O : std_logic;
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-- signals to remember, whether the previous read cycle
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-- addressed internal memory or external memory
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--
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signal OPCS : std_logic; -- '1' if opcode from external memory
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signal RDATS : std_logic; -- '1' if data from external memory
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signal EXTERN : std_logic; -- '1' if opcode or data from external memory
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begin
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begin
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memo: memory
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memo: memory
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => LT2,
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T2 => T2,
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CE => CE,
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CE => CE,
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-- read in T1
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-- read in T1
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PC => M_PC,
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PC => M_PC,
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OPC => LM_OPC,
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OPC => LM_OPC,
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-- read or written in T2
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-- read or written in T2
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ADR => ADR,
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ADR => ADR,
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WR => MEM_WE,
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WR => LM_WE,
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WDAT => MEM_WDAT,
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WDAT => WDAT,
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RDAT => LM_RDAT
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RDAT => LM_RDAT
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);
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);
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ocf: opcode_fetch
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ocf: opcode_fetch
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => LT2,
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T2 => T2,
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CLR => CLR,
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CLR => RST_I,
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CE => CE,
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CE => CE,
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PC_OP => D_PC_OP,
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PC_OP => D_PC_OP,
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JDATA => OC_JD,
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JDATA => OC_JD,
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RR => C_RR,
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RR => C_RR,
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RDATA => MEM_RDAT,
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RDATA => RDAT,
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PC => M_PC
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PC => M_PC
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);
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);
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opdec: opcode_decoder
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opdec: opcode_decoder
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => LT2,
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T2 => T2,
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CLR => CLR,
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CLR => RST_I,
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CE => CE,
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CE => CE,
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OPCODE => D_OPC,
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OPCODE => D_OPC,
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OP_CYC => D_CYC,
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OP_CYC => D_CYC,
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INT => INT,
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INT => INT,
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RRZ => RRZ,
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RRZ => RRZ,
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OP_CAT => D_CAT,
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OP_CAT => D_CAT,
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-- select signals
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-- select signals
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D_SX => D_SX,
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D_SX => D_SX,
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D_SY => D_SY,
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D_SY => D_SY,
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D_OP => D_OP,
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D_OP => D_OP,
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D_SA => D_SA,
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D_SA => D_SA,
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D_SMQ => D_SMQ,
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D_SMQ => D_SMQ,
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-- write enable/select signal
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-- write enable/select signal
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D_WE_RR => D_WE_RR,
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D_WE_RR => D_WE_RR,
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D_WE_LL => D_WE_LL,
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D_WE_LL => D_WE_LL,
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D_WE_M => D_MEM_WE,
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D_WE_SP => D_WE_SP,
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D_WE_SP => D_WE_SP,
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D_RD_O => D_RD_O,
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D_WE_O => D_WE_O,
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D_LOCK => D_LOCK,
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IO_RD => D_IO_RD,
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D_IO => D_IO,
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IO_WR => D_IO_WR,
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PC_OP => D_PC_OP,
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PC_OP => D_PC_OP,
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LAST_M => D_LAST_M,
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LAST_M => D_LAST_M,
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HLT => HALT
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HLT => HALT
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);
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);
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dcore: data_core
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dcore: data_core
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => LT2,
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T2 => T2,
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CLR => CLR,
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CLR => RST_I,
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CE => CE,
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CE => CE,
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|
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-- select signals
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-- select signals
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SX => C_SX,
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SX => C_SX,
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SY => C_SY,
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SY => C_SY,
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| Line 300... |
Line 317... |
WE_RR => C_WE_RR,
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WE_RR => C_WE_RR,
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WE_LL => C_WE_LL,
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WE_LL => C_WE_LL,
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WE_SP => C_WE_SP,
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WE_SP => C_WE_SP,
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|
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IMM => C_IMM,
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IMM => C_IMM,
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M_RDAT => MEM_RDAT,
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RDAT => RDAT,
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ADR => ADR,
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ADR => ADR,
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MQ => MEM_WDAT,
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MQ => WDAT,
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IO_RDAT => IO_RDAT,
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Q_RR => C_RR,
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Q_RR => C_RR,
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Q_LL => Q_LL,
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Q_LL => Q_LL,
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Q_SP => Q_SP
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Q_SP => Q_SP
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);
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);
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|
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CE <= '1';
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CE <= ACK_I or not EXTERN;
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T2 <= LT2;
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TGA_O(0) <= T2 and C_IO;
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WE_O <= T2 and C_WE_O;
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STB_O <= EXTERN;
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CYC_O <= EXTERN;
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IO_ADR <= ADR(7 downto 0);
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Q_RR <= C_RR;
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Q_RR <= C_RR;
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RRZ <= '1' when (C_RR = X"0000") else '0';
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RRZ <= '1' when (C_RR = X"0000") else '0';
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OC_JD <= M_OPC & C_IMM(7 downto 0);
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OC_JD <= M_OPC & C_IMM(7 downto 0);
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Q_PC <= C_PC;
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Q_PC <= C_PC;
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| Line 331... |
Line 348... |
Q_SY <= C_SY;
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Q_SY <= C_SY;
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Q_OP <= C_OP;
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Q_OP <= C_OP;
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Q_SA <= C_SA;
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Q_SA <= C_SA;
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Q_SMQ <= C_SMQ;
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Q_SMQ <= C_SMQ;
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-- write enable/select signal
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-- write enable/select signal (debug)
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Q_WE_RR <= C_WE_RR;
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Q_WE_RR <= C_WE_RR;
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Q_WE_LL <= C_WE_LL;
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Q_WE_LL <= C_WE_LL;
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Q_WE_SP <= C_WE_SP;
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Q_WE_SP <= C_WE_SP;
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|
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XM_WDAT <= MEM_WDAT;
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DAT_O <= WDAT;
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|
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process(CLK_I)
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process(CLK_I)
|
begin
|
begin
|
if (rising_edge(CLK_I)) then
|
if (rising_edge(CLK_I)) then
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LT2 <= not LT2;
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if (RST_I = '1') then T2 <= '0';
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else T2 <= not T2;
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end if;
|
end if;
|
end if;
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end process;
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end process;
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|
|
process(CLK_I)
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process(T2, M_PC, ADR, C_IO)
|
begin
|
begin
|
if (rising_edge(CLK_I)) then
|
if (T2 = '0') then -- opcode fetch
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if (LT2 = '1') then
|
EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
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RDATS <= ADR(15) or ADR(14) or ADR(13);
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-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
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LXM_RDAT <= XM_RDAT;
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-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
|
end if;
|
-- B EXTERN <= '1'; -- no internal memory
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else -- data or I/O
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EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 8Kx8 internal memory
|
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-- A EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 512x8 internal memory
|
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-- A ADR(12) or ADR(11) or ADR(10) or ADR(9) or
|
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-- B EXTERN <= ('1' or -- no internal memory
|
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C_IO) and (C_RD_O or C_WE_O);
|
end if;
|
end if;
|
end process;
|
end process;
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|
|
|
-- remember whether access is to internal or to external (incl I/O) memory.
|
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-- clock read data to XM_OPCODE in T1 or to XM_RDAT in T2
|
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--
|
process(CLK_I)
|
process(CLK_I)
|
begin
|
begin
|
if (rising_edge(CLK_I)) then
|
if (rising_edge(CLK_I)) then
|
if (LT2 = '0') then
|
if (T2 = '0') then
|
OPCS <= M_PC(15) or M_PC(14) or M_PC(13);
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OPCS <= EXTERN;
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XM_OPC <= XM_RDAT;
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XM_OPC <= DAT_I;
|
end if;
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else
|
end if;
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RDATS <= EXTERN;
|
end process;
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XM_RDAT <= DAT_I;
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|
|
process(OPCS, LM_OPC, XM_OPC)
|
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begin
|
|
if (OPCS = '0') then M_OPC <= LM_OPC;
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else M_OPC <= XM_OPC;
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|
end if;
|
end if;
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end process;
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|
|
|
process(RDATS, LXM_RDAT, LM_RDAT)
|
|
begin
|
|
if (RDATS = '0') then MEM_RDAT <= LM_RDAT;
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else MEM_RDAT <= LXM_RDAT;
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
process(LT2, M_PC, ADR, MEM_WE)
|
M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
|
begin
|
ADR_O <= M_PC when (T2 = '0') else ADR;
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if (LT2 = '0') then -- opcode fetch
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RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
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XM_ADR <= M_PC;
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XM_WE <= '0';
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XM_CE <= M_PC(15) or M_PC(14) or M_PC(13);
|
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else -- data
|
|
XM_ADR <= ADR;
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XM_WE <= MEM_WE;
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XM_CE <= ADR(15) or ADR(14) or ADR(13);
|
|
end if;
|
|
end process;
|
|
|
|
process(CLK_I)
|
process(CLK_I)
|
begin
|
begin
|
if (rising_edge(CLK_I)) then
|
if (rising_edge(CLK_I)) then
|
if (LT2 = '1') then
|
if (RST_I = '1') then
|
if (CLR = '1') then
|
|
D_PC <= X"0000";
|
D_PC <= X"0000";
|
D_OPC <= X"01";
|
D_OPC <= X"01";
|
D_CYC <= M1;
|
D_CYC <= M1;
|
|
|
C_PC <= X"0000";
|
C_PC <= X"0000";
|
| Line 414... |
Line 421... |
C_SA <= "00000";
|
C_SA <= "00000";
|
C_SMQ <= '0';
|
C_SMQ <= '0';
|
C_WE_RR <= '0';
|
C_WE_RR <= '0';
|
C_WE_LL <= '0';
|
C_WE_LL <= '0';
|
C_WE_SP <= SP_NOP;
|
C_WE_SP <= SP_NOP;
|
MEM_WE <= '0';
|
C_IO <= '0';
|
|
C_RD_O <= '0';
|
elsif (CE = '1') then
|
C_WE_O <= '0';
|
|
LM_WE <= '0';
|
|
elsif (CE = '1' and T2 = '1') then
|
C_CYC <= D_CYC;
|
C_CYC <= D_CYC;
|
Q_CAT <= D_CAT;
|
Q_CAT <= D_CAT;
|
C_PC <= D_PC;
|
C_PC <= D_PC;
|
C_OPC <= D_OPC;
|
C_OPC <= D_OPC;
|
C_SX <= D_SX;
|
C_SX <= D_SX;
|
| Line 429... |
Line 438... |
C_SA <= D_SA;
|
C_SA <= D_SA;
|
C_SMQ <= D_SMQ;
|
C_SMQ <= D_SMQ;
|
C_WE_RR <= D_WE_RR;
|
C_WE_RR <= D_WE_RR;
|
C_WE_LL <= D_WE_LL;
|
C_WE_LL <= D_WE_LL;
|
C_WE_SP <= D_WE_SP;
|
C_WE_SP <= D_WE_SP;
|
IO_RD <= D_IO_RD;
|
C_IO <= D_IO;
|
IO_WR <= D_IO_WR;
|
C_RD_O <= D_RD_O;
|
MEM_WE <= D_MEM_WE;
|
C_WE_O <= D_WE_O;
|
|
LM_WE <= D_WE_O and not D_IO;
|
|
|
if (D_LAST_M = '1') then -- D goes to M1
|
if (D_LAST_M = '1') then -- D goes to M1
|
-- signals valid for entire opcode...
|
-- signals valid for entire opcode...
|
D_OPC <= M_OPC;
|
D_OPC <= M_OPC;
|
D_PC <= M_PC;
|
D_PC <= M_PC;
|
| Line 451... |
Line 461... |
when M5 => D_CYC <= M1;
|
when M5 => D_CYC <= M1;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
No newline at end of file
|
No newline at end of file
|
