| Line 19... |
Line 19... |
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ARCHITECTURE behavior OF testbench IS
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ARCHITECTURE behavior OF testbench IS
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COMPONENT cpu16
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COMPONENT cpu16
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PORT(
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PORT(
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clk : IN std_logic;
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clk_i : IN std_logic;
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cck : IN std_logic;
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switch : IN std_logic_vector(9 downto 0);
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switch : IN std_logic_vector(9 downto 0);
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ser_in : IN std_logic;
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ser_in : IN std_logic;
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temp_spo : IN std_logic;
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temp_spo : IN std_logic;
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xm_rdat : IN std_logic_vector(7 downto 0);
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xm_rdat : IN std_logic_vector(7 downto 0);
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ser_out : OUT std_logic;
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ser_out : OUT std_logic;
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| Line 39... |
Line 38... |
xm_we : OUT std_logic;
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xm_we : OUT std_logic;
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xm_ce : OUT std_logic
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xm_ce : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal clk : std_logic;
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signal clk_i : std_logic;
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signal cck : std_logic;
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signal switch : std_logic_vector(9 downto 0) := "0000000000";
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signal switch : std_logic_vector(9 downto 0) := "0000000000";
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signal ser_in : std_logic := '0';
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signal ser_in : std_logic := '0';
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signal temp_spo : std_logic := '0';
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signal temp_spo : std_logic := '0';
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signal xm_rdat : std_logic_vector(7 downto 0) := X"33";
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signal xm_rdat : std_logic_vector(7 downto 0) := X"33";
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signal ser_out : std_logic;
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signal ser_out : std_logic;
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Line 60... |
signal clk_counter : INTEGER := 0;
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signal clk_counter : INTEGER := 0;
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BEGIN
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BEGIN
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uut: cpu16 PORT MAP(
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uut: cpu16 PORT MAP(
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clk => clk,
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clk_i => clk_i,
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cck => cck,
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switch => switch,
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switch => switch,
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ser_in => ser_in,
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ser_in => ser_in,
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ser_out => ser_out,
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ser_out => ser_out,
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temp_spo => temp_spo,
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temp_spo => temp_spo,
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temp_spi => temp_spi,
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temp_spi => temp_spi,
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Line 82... |
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-- *** Test Bench - User Defined Section ***
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-- *** Test Bench - User Defined Section ***
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PROCESS -- clock process for CLK,
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PROCESS -- clock process for CLK,
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BEGIN
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BEGIN
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CLOCK_LOOP : LOOP
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CLOCK_LOOP : LOOP
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CLK <= transport '0';
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CLK_I <= transport '0';
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WAIT FOR 1 ns;
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WAIT FOR 1 ns;
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CLK <= transport '1';
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CLK_I <= transport '1';
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WAIT FOR 1 ns;
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WAIT FOR 1 ns;
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WAIT FOR 11 ns;
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WAIT FOR 11 ns;
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CLK <= transport '0';
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CLK_I <= transport '0';
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WAIT FOR 12 ns;
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WAIT FOR 12 ns;
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END LOOP CLOCK_LOOP;
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END LOOP CLOCK_LOOP;
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END PROCESS;
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END PROCESS;
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PROCESS(CLK)
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PROCESS(CLK_I)
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BEGIN
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BEGIN
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if (rising_edge(CLK)) then
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if (rising_edge(CLK_I)) then
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CLK_COUNTER <= CLK_COUNTER + 1;
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CLK_COUNTER <= CLK_COUNTER + 1;
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case CLK_COUNTER is
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case CLK_COUNTER is
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when 0 => switch(9 downto 8) <= "11";
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when 0 => switch(9 downto 8) <= "11";
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when 1 => switch(9 downto 8) <= "00";
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when 1 => switch(9 downto 8) <= "00";
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