| Line 30... |
Line 30... |
WE_LL : in std_logic;
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WE_LL : in std_logic;
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WE_SP : in SP_OP;
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WE_SP : in SP_OP;
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|
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-- data in signals
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-- data in signals
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IMM : in std_logic_vector(15 downto 0); -- immediate data
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IMM : in std_logic_vector(15 downto 0); -- immediate data
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M_RDAT : in std_logic_vector( 7 downto 0); -- memory data
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RDAT : in std_logic_vector( 7 downto 0); -- memory/IO data
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|
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-- memory control signals
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-- memory control signals
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ADR : out std_logic_vector(15 downto 0);
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ADR : out std_logic_vector(15 downto 0);
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MQ : out std_logic_vector( 7 downto 0);
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MQ : out std_logic_vector( 7 downto 0);
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|
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-- input/output
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IO_RDAT: in std_logic_vector( 7 downto 0);
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|
|
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Q_RR : out std_logic_vector(15 downto 0);
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Q_RR : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_SP : out std_logic_vector(15 downto 0)
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Q_SP : out std_logic_vector(15 downto 0)
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);
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);
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end data_core;
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end data_core;
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| Line 69... |
Line 66... |
|
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COMPONENT select_yy
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COMPONENT select_yy
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PORT( SY : IN std_logic_vector( 3 downto 0);
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PORT( SY : IN std_logic_vector( 3 downto 0);
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IMM : IN std_logic_vector(15 downto 0);
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IMM : IN std_logic_vector(15 downto 0);
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QUICK : IN std_logic_vector( 3 downto 0);
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QUICK : IN std_logic_vector( 3 downto 0);
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M_RDAT : IN std_logic_vector( 7 downto 0);
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RDAT : IN std_logic_vector( 7 downto 0);
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IO_RDAT : IN std_logic_vector( 7 downto 0);
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RR : IN std_logic_vector(15 downto 0);
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RR : IN std_logic_vector(15 downto 0);
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YY : OUT std_logic_vector(15 downto 0)
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YY : OUT std_logic_vector(15 downto 0)
|
);
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);
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END COMPONENT;
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END COMPONENT;
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| Line 109... |
Line 105... |
|
|
selyy: select_yy
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selyy: select_yy
|
PORT MAP( SY => SY,
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PORT MAP( SY => SY,
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IMM => IMM,
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IMM => IMM,
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QUICK => QU,
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QUICK => QU,
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M_RDAT => M_RDAT,
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RDAT => RDAT,
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IO_RDAT => IO_RDAT,
|
|
RR => RR,
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RR => RR,
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YY => YY
|
YY => YY
|
);
|
);
|
|
|
ADR <= ADR_XYZ;
|
ADR <= ADR_XYZ;
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| Line 177... |
Line 172... |
end process;
|
end process;
|
|
|
regs: process(CLK_I)
|
regs: process(CLK_I)
|
begin
|
begin
|
if (rising_edge(CLK_I)) then
|
if (rising_edge(CLK_I)) then
|
if (T2 = '1') then
|
|
if (CLR = '1') then
|
if (CLR = '1') then
|
RR <= X"0000";
|
RR <= X"0000";
|
LL <= X"0000";
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LL <= X"0000";
|
SP <= X"0000";
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SP <= X"0000";
|
elsif (CE = '1') then
|
elsif (CE = '1' and T2 = '1') then
|
if (WE_RR = '1') then RR <= ZZ; end if;
|
if (WE_RR = '1') then RR <= ZZ; end if;
|
if (WE_LL = '1') then LL <= ZZ; end if;
|
if (WE_LL = '1') then LL <= ZZ; end if;
|
|
|
case WE_SP is
|
case WE_SP is
|
when SP_INC => SP <= ADR_YZ;
|
when SP_INC => SP <= ADR_YZ;
|
when SP_LOAD => SP <= ADR_XYZ;
|
when SP_LOAD => SP <= ADR_XYZ;
|
when SP_NOP => null;
|
when SP_NOP => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
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No newline at end of file
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No newline at end of file
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