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[/] [c16/] [trunk/] [vhdl/] [ds1722.vhd] - Diff between revs 2 and 9
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Rev 9 |
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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entity DS1722 is
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entity DS1722 is
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Port( CLK_I: in std_logic;
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Port( CLK_I: in std_logic;
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T2: in std_logic;
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RST_I: in std_logic;
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RESET: in std_logic;
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DATA_IN: in std_logic_vector(7 downto 0);
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DATA_IN: in std_logic_vector(7 downto 0);
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DATA_OUT: out std_logic_vector(7 downto 0);
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DATA_OUT: out std_logic_vector(7 downto 0);
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ADDRESS: in std_logic_vector(7 downto 0);
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ADDRESS: in std_logic_vector(7 downto 0);
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signal Write: std_logic;
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signal Write: std_logic;
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begin
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begin
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-- Set up counter to sample digital themometer.
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-- divide CLK_I by 256
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process (CLK_I, RESET)
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--
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process (CLK_I)
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begin
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begin
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if (RESET = '1') then --asynchronous RESET active High
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if (rising_edge(CLK_I)) then
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counter <= "00000000";
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if (RST_I = '1') then counter <= "00000000";
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elsif (rising_edge(CLK_I)) then
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else counter <= counter + "00000001";
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if (T2 = '1') then
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counter <= counter + "00000001";
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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DONE <= START when (state = LAST_ONE) else '0';
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DONE <= START when (state = LAST_ONE) else '0';
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DATA_OUT <= data_latch;
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DATA_OUT <= data_latch;
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Write <= ADDRESS(7);
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Write <= ADDRESS(7);
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-- process to convert byte commands to SPI and SPI to byte.
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-- convert byte commands to SPI and SPI to byte.
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process (CLK_I, RESET)
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--
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process (CLK_I)
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begin
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begin
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if (RESET='1') then --asynchronous RESET active High
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if (rising_edge(CLK_I)) then
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if (RST_I = '1') then
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state <= SET_CE;
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state <= SET_CE;
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TEMP_CE <= '0';
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TEMP_CE <= '0';
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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bit_count <= 0;
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bit_count <= 0;
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elsif (rising_edge(CLK_I)) then
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elsif (counter = "11111111" and START = '1') then
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if (T2 = '1') then
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if (counter = "11111111" and START = '1') then
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case state is
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case state is
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when SET_CE =>
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when SET_CE =>
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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TEMP_CE <= '1';
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TEMP_CE <= '1';
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state <= LATCH_ADD;
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state <= LATCH_ADD;
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TEMP_SCLK <= '0';
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TEMP_SCLK <= '0';
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state <= SET_CE;
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state <= SET_CE;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end DS1722_arch;
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end DS1722_arch;
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