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use work.cpu_pack.ALL;
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use work.cpu_pack.ALL;
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entity input_output is
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entity input_output is
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PORT ( CLK_I : in std_logic;
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PORT ( CLK_I : in std_logic;
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T2 : in std_logic;
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ADR_I : in std_logic_vector( 7 downto 0);
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CYC_I : in std_logic;
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STB_I : in std_logic;
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ACK_O : out std_logic;
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RST_O : out STD_LOGIC;
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SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
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SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
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HALT : in STD_LOGIC;
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HALT : in STD_LOGIC;
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SER_IN : in STD_LOGIC;
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SER_IN : in STD_LOGIC;
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SER_OUT : out STD_LOGIC;
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SER_OUT : out STD_LOGIC;
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| Line 25... |
Line 31... |
TEMP_CE : out STD_LOGIC;
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TEMP_CE : out STD_LOGIC;
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TEMP_SCLK : out STD_LOGIC;
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TEMP_SCLK : out STD_LOGIC;
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LED : out STD_LOGIC_VECTOR (7 downto 0);
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LED : out STD_LOGIC_VECTOR (7 downto 0);
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CLR : out STD_LOGIC;
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-- input/output
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-- input/output
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IO_RD : in std_logic;
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IO : in std_logic;
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IO_WR : in std_logic;
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WE_I : in std_logic;
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IO_ADR : in std_logic_vector( 7 downto 0);
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IO_RDAT : out std_logic_vector( 7 downto 0);
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IO_RDAT : out std_logic_vector( 7 downto 0);
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IO_WDAT : in std_logic_vector( 7 downto 0);
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IO_WDAT : in std_logic_vector( 7 downto 0);
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INT : out STD_LOGIC
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INT : out STD_LOGIC
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);
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);
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end input_output;
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end input_output;
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architecture Behavioral of input_output is
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architecture Behavioral of input_output is
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COMPONENT temperature
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COMPONENT temperature
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PORT( CLK_I : IN std_logic;
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PORT( CLK_I : IN std_logic;
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T2 : IN std_logic;
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RST_I : IN std_logic;
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CLR : IN std_logic;
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TEMP_SPO : IN std_logic;
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TEMP_SPO : IN std_logic;
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DATA_OUT : OUT std_logic_vector(7 downto 0);
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DATA_OUT : OUT std_logic_vector(7 downto 0);
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TEMP_SPI : OUT std_logic;
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TEMP_SPI : OUT std_logic;
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TEMP_CE : OUT std_logic;
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TEMP_CE : OUT std_logic;
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TEMP_SCLK : OUT std_logic
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TEMP_SCLK : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT uart_baudgen
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COMPONENT uart_baudgen
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PORT( CLK_I : IN std_logic;
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PORT( CLK_I : IN std_logic;
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T2 : IN std_logic;
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RST_I : IN std_logic;
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CLR : IN std_logic;
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RD : IN std_logic;
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RD : IN std_logic;
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WR : IN std_logic;
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WR : IN std_logic;
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TX_DATA : IN std_logic_vector(7 downto 0);
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TX_DATA : IN std_logic_vector(7 downto 0);
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RX_SERIN : IN std_logic;
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RX_SERIN : IN std_logic;
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TX_SEROUT : OUT std_logic;
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TX_SEROUT : OUT std_logic;
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| Line 66... |
Line 67... |
RX_READY : OUT std_logic;
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RX_READY : OUT std_logic;
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TX_BUSY : OUT std_logic
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TX_BUSY : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal L_IO_ADR : std_logic_vector(7 downto 0);
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signal IO_RD_SERIAL : std_logic;
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signal IO_RD_SERIAL : std_logic;
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signal IO_WR_SERIAL : std_logic;
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signal IO_WR_SERIAL : std_logic;
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signal RX_READY : std_logic;
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signal RX_READY : std_logic;
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signal TX_BUSY : std_logic;
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signal TX_BUSY : std_logic;
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signal RX_DATA : std_logic_vector(7 downto 0);
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signal RX_DATA : std_logic_vector(7 downto 0);
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signal TEMP_DO : std_logic_vector(7 downto 0);
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signal TEMP_DO : std_logic_vector(7 downto 0);
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signal FLAG : std_logic;
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signal SERDAT : std_logic;
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signal LCLR : std_logic;
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signal LCLR : std_logic;
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signal C1_N, C2_N : std_logic; -- switch debounce, active low
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signal C1_N, C2_N : std_logic; -- switch debounce, active low
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signal RX_INT_ENABLED : std_logic;
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signal RX_INT_ENABLED : std_logic;
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signal TX_INT_ENABLED : std_logic;
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signal TX_INT_ENABLED : std_logic;
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signal TIM_INT_ENABLED : std_logic;
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signal TIM_INT_ENABLED : std_logic;
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signal TIMER_INT : std_logic;
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signal TIMER_INT : std_logic;
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signal TIMER : std_logic_vector(14 downto 0);
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signal TIMER : std_logic_vector(15 downto 0);
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signal CLK_COUNT : std_logic_vector(15 downto 0);
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signal CLK_COUNT : std_logic_vector(16 downto 0);
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signal CLK_COUNT_EN : std_logic;
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signal CLK_COUNT_EN : std_logic;
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signal CLK_HALT_MSK : std_logic;
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signal CLK_HALT_MSK : std_logic;
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signal CLK_HALT_VAL : std_logic;
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signal CLK_HALT_VAL : std_logic;
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begin
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begin
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tempr: temperature
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tempr: temperature
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => T2,
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RST_I => LCLR,
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CLR => LCLR,
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DATA_OUT => TEMP_DO,
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DATA_OUT => TEMP_DO,
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TEMP_SPI => TEMP_SPI,
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TEMP_SPI => TEMP_SPI,
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TEMP_SPO => TEMP_SPO,
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TEMP_SPO => TEMP_SPO,
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TEMP_CE => TEMP_CE,
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TEMP_CE => TEMP_CE,
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TEMP_SCLK => TEMP_SCLK
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TEMP_SCLK => TEMP_SCLK
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);
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);
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uart: uart_baudgen
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uart: uart_baudgen
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => T2,
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RST_I => LCLR,
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CLR => LCLR,
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RD => IO_RD_SERIAL,
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RD => IO_RD_SERIAL,
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WR => IO_WR_SERIAL,
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WR => IO_WR_SERIAL,
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TX_DATA => IO_WDAT,
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TX_DATA => IO_WDAT,
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TX_SEROUT => SER_OUT,
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TX_SEROUT => SER_OUT,
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RX_SERIN => SER_IN,
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RX_SERIN => SER_IN,
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RX_DATA => RX_DATA,
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RX_DATA => RX_DATA,
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RX_READY => RX_READY,
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RX_READY => RX_READY,
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TX_BUSY => TX_BUSY
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TX_BUSY => TX_BUSY
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);
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);
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CLR <= LCLR;
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RST_O <= LCLR;
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INT <= (RX_INT_ENABLED and RX_READY)
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INT <= (RX_INT_ENABLED and RX_READY)
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or (TX_INT_ENABLED and not TX_BUSY)
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or (TX_INT_ENABLED and not TX_BUSY)
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or (TIM_INT_ENABLED and TIMER_INT);
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or (TIM_INT_ENABLED and TIMER_INT);
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SERDAT <= (IO and CYC_I) when (ADR_I = X"00") else '0';
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IO_RD_SERIAL <= SERDAT and not WE_I;
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IO_WR_SERIAL <= SERDAT and WE_I;
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ACK_O <= STB_I;
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-- IO read process
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-- IO read process
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--
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--
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process(L_IO_ADR, IO_RD, IO_WR, RX_DATA, TEMP_DO, SWITCH,
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process(ADR_I, RX_DATA, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
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TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
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RX_INT_ENABLED, RX_READY, TEMP_DO, SWITCH, CLK_COUNT)
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RX_INT_ENABLED, RX_READY)
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begin
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begin
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IO_RD_SERIAL <= '0';
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case ADR_I is
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IO_WR_SERIAL <= '0';
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case L_IO_ADR is
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when X"00" => IO_RDAT <= RX_DATA;
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when X"00" => IO_RDAT <= RX_DATA;
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IO_RD_SERIAL <= IO_RD;
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IO_WR_SERIAL <= IO_WR;
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when X"01" => IO_RDAT <= '0'
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when X"01" => IO_RDAT <= '0'
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& (TIM_INT_ENABLED and TIMER_INT)
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& (TIM_INT_ENABLED and TIMER_INT)
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& (TX_INT_ENABLED and not TX_BUSY)
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& (TX_INT_ENABLED and not TX_BUSY)
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& (RX_INT_ENABLED and RX_READY)
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& (RX_INT_ENABLED and RX_READY)
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& '0'
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& '0'
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& TIMER_INT
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& TIMER_INT
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& TX_BUSY
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& TX_BUSY
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& RX_READY;
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& RX_READY;
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when X"02" => IO_RDAT <= TEMP_DO;
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when X"02" => IO_RDAT <= TEMP_DO;
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when X"03" => IO_RDAT <= SWITCH(7 downto 0);
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when X"03" => IO_RDAT <= SWITCH(7 downto 0);
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when X"05" => IO_RDAT <= CLK_COUNT(7 downto 0);
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when X"05" => IO_RDAT <= CLK_COUNT(8 downto 1);
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when others => IO_RDAT <= CLK_COUNT(15 downto 8);
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when others => IO_RDAT <= CLK_COUNT(16 downto 9);
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end case;
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end case;
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end process;
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end process;
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-- IO write and timer process
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-- IO write and timer process
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--
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--
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process(CLK_I)
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process(CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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if (T2 = '1') then
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L_IO_ADR <= IO_ADR;
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if (LCLR = '1') then
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if (LCLR = '1') then
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LED <= X"00";
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LED <= X"00";
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RX_INT_ENABLED <= '0';
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RX_INT_ENABLED <= '0';
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TX_INT_ENABLED <= '0';
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TX_INT_ENABLED <= '0';
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TIM_INT_ENABLED <= '0';
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TIM_INT_ENABLED <= '0';
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TIMER_INT <= '0';
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TIMER_INT <= '0';
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TIMER <= "000" & X"000";
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TIMER <= X"0000";
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else
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else
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if (IO_WR = '1') then
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if (IO = '1' and CYC_I = '1' and WE_I = '1') then
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case L_IO_ADR is
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case ADR_I is
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when X"00" => -- handled by uart
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when X"00" => -- handled by uart
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when X"01" => -- handled by uart
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when X"01" => -- handled by uart
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when X"02" => LED <= IO_WDAT;
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when X"02" => LED <= IO_WDAT;
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when X"03" => RX_INT_ENABLED <= IO_WDAT(0);
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when X"03" => RX_INT_ENABLED <= IO_WDAT(0);
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TX_INT_ENABLED <= IO_WDAT(1);
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TX_INT_ENABLED <= IO_WDAT(1);
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TIM_INT_ENABLED <= IO_WDAT(2);
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TIM_INT_ENABLED <= IO_WDAT(2);
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when X"04" => TIMER_INT <= '0';
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when X"04" => TIMER_INT <= '0';
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when X"05" => CLK_COUNT_EN <= '1';
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when X"05" => CLK_COUNT_EN <= '1';
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CLK_COUNT <= X"0000";
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CLK_COUNT <= '0' & X"0000";
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CLK_HALT_VAL <= IO_WDAT(0);
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CLK_HALT_VAL <= IO_WDAT(0);
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CLK_HALT_MSK <= IO_WDAT(1);
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CLK_HALT_MSK <= IO_WDAT(1);
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when X"06" => CLK_COUNT_EN <= '0';
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when X"06" => CLK_COUNT_EN <= '0';
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when others =>
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when others =>
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end case;
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end case;
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end if;
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end if;
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TIMER <= TIMER + 1;
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if (TIMER = 39999) then -- 1 ms at 40 MHz
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if (TIMER = 19999) then -- 1 ms
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TIMER_INT <= '1';
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TIMER_INT <= '1';
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TIMER <= "000" & X"000";
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TIMER <= X"0000";
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else
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TIMER <= TIMER + 1;
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end if;
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end if;
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if (CLK_COUNT_EN = '1' and
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if (CLK_COUNT_EN = '1' and
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(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
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(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
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CLK_COUNT <= CLK_COUNT + 1;
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CLK_COUNT <= CLK_COUNT + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- reset debounce process
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-- reset debounce process
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--
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--
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process(CLK_I)
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process(CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I)) then
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if (T2 = '1') then
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-- switch debounce
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-- switch debounce
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if (SWITCH(8) = '1' or SWITCH(9) = '1') then
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if (SWITCH(8) = '1' or SWITCH(9) = '1') then
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LCLR <= '1';
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LCLR <= '1';
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C2_N <= '0';
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C2_N <= '0';
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C1_N <= '0';
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C1_N <= '0';
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| Line 214... |
Line 209... |
LCLR <= not C2_N;
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LCLR <= not C2_N;
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C2_N <= C1_N;
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C2_N <= C1_N;
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C1_N <= '1';
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C1_N <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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