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https://opencores.org/ocsvn/c16/c16/trunk
[/] [c16/] [trunk/] [vhdl/] [memory.vhd] - Diff between revs 2 and 21
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| Rev 2 |
Rev 21 |
| Line 325... |
Line 325... |
RSTA => '0', RSTB => '0',
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RSTA => '0', RSTB => '0',
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WEA => '0', WEB => WR_1,
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WEA => '0', WEB => WR_1,
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DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)
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DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)
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);
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);
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process(CLK_I)
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process(CLK_I) -- new
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I) and T2 = '1') then
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if (T2 = '1') then
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if (CE = '1') then
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if (CE = '1') then
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LADR <= ADR(15 downto 12);
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LADR <= ADR(15 downto 12);
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(LADR, OUT_0, OUT_1)
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process(LADR, OUT_0, OUT_1)
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begin
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begin
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|
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case LADR is
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case LADR is
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when "0001" => RDAT <= OUT_1;
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when "0001" => RDAT <= OUT_1;
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| Line 348... |
Line 347... |
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end process;
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end process;
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process(CLK_I)
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process(CLK_I)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (rising_edge(CLK_I) and T2 = '0') then
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if (T2 = '0') then
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if (CE = '1') then
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if (CE = '1') then
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LPC <= PC(15 downto 12);
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LPC <= PC(15 downto 12);
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(LPC, OPC_0, OPC_1)
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process(LPC, OPC_0, OPC_1)
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begin
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begin
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case LPC is
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case LPC is
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