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[/] [c16/] [trunk/] [vhdl/] [opcode_decoder.vhd] - Diff between revs 17 and 21
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| Rev 17 |
Rev 21 |
| Line 96... |
Line 96... |
LAST_M <= '1' when (OP_CYC = LAST) else '0';
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LAST_M <= '1' when (OP_CYC = LAST) else '0';
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HLT <= HALTED; -- show when CPU is halted
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HLT <= HALTED; -- show when CPU is halted
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-- HLT <= '1' when DISABLE_CNT = 0 else '0'; -- show when ints enabled
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-- HLT <= '1' when DISABLE_CNT = 0 else '0'; -- show when ints enabled
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process(CLK_I)
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process(CLK_I, CLR)
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begin
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begin
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if (rising_edge(CLK_I)) then
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if (CLR = '1') then
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if (CLR = '1') then
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DISABLE_CNT <= "0001"; -- 1 x disabled
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DISABLE_CNT <= "0001"; -- 1 x disabled
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INT_M2 <= '0';
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INT_M2 <= '0';
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HALTED <= '0';
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HALTED <= '0';
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elsif (CE = '1' and T2 = '1') then
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elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
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if (DISABLE_INT = '1') then
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if (DISABLE_INT = '1') then
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DISABLE_CNT <= DISABLE_CNT + 1;
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DISABLE_CNT <= DISABLE_CNT + 1;
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elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then
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elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then
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DISABLE_CNT <= DISABLE_CNT - 1;
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DISABLE_CNT <= DISABLE_CNT - 1;
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end if;
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end if;
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| Line 118... |
Line 117... |
HALTED <= '1';
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HALTED <= '1';
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end if;
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end if;
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INT_M2 <= INT_M1;
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INT_M2 <= INT_M1;
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end if;
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end if;
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end if;
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end process;
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end process;
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process(OPCODE, OP_CYC, INT, RRZ, INT_M2, DISABLE_CNT, HALTED)
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process(OPCODE, OP_CYC, INT, RRZ, INT_M2, DISABLE_CNT, HALTED)
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variable IS_M1 : std_logic;
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variable IS_M1 : std_logic;
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