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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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entity temperature is
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entity temperature is
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PORT( CLK_I : in STD_LOGIC;
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PORT( CLK_I : in STD_LOGIC;
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T2 : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CLR : in STD_LOGIC;
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DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0);
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DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0);
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TEMP_SPI : out STD_LOGIC;
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TEMP_SPI : out STD_LOGIC;
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TEMP_SPO : in STD_LOGIC;
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TEMP_SPO : in STD_LOGIC;
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TEMP_CE : out STD_LOGIC;
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TEMP_CE : out STD_LOGIC;
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TEMP_SCLK : out STD_LOGIC
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TEMP_SCLK : out STD_LOGIC
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end temperature;
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end temperature;
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architecture behavioral of temperature is
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architecture behavioral of temperature is
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component DS1722
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component DS1722
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PORT( RESET : in std_logic;
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PORT( CLK_I : in std_logic;
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CLK_I : in std_logic;
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RST_I : in std_logic;
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T2 : in std_logic;
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DATA_IN : in std_logic_vector(7 downto 0);
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DATA_IN : in std_logic_vector(7 downto 0);
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DATA_OUT : out std_logic_vector(7 downto 0);
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DATA_OUT : out std_logic_vector(7 downto 0);
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ADDRESS : in std_logic_vector(7 downto 0);
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ADDRESS : in std_logic_vector(7 downto 0);
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begin
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begin
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tsensor: DS1722
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tsensor: DS1722
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PORT MAP( CLK_I => CLK_I,
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PORT MAP( CLK_I => CLK_I,
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T2 => T2,
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RST_I => RST_I,
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RESET => CLR,
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DATA_IN => TEMP_DATA_IN,
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DATA_IN => TEMP_DATA_IN,
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DATA_OUT => TEMP_DATA_OUT,
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DATA_OUT => TEMP_DATA_OUT,
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ADDRESS => TEMP_ADDRESS,
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ADDRESS => TEMP_ADDRESS,
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TEMP_SPO => TEMP_SPO,
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TEMP_SPO => TEMP_SPO,
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TEMP_CE => TEMP_CE,
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TEMP_CE => TEMP_CE,
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TEMP_SCLK => TEMP_SCLK
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TEMP_SCLK => TEMP_SCLK
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);
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);
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-- State machine to step though the process of getting data from the Digital Thermometer.
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-- State machine to step though the process of getting data
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process (CLR, CLK_I)
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-- from the Digital Thermometer.
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--
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process (CLK_I)
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begin
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begin
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if (CLR = '1') then
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if (rising_edge(CLK_I)) then
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if (RST_I = '1') then
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TEMP_state <= TEMP_IDLE;
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TEMP_state <= TEMP_IDLE;
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TEMP_START <= '0';
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TEMP_START <= '0';
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TEMP_ADDRESS <= "00000000";
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TEMP_ADDRESS <= "00000000";
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TEMP_DATA_IN <= "00000000";
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TEMP_DATA_IN <= "00000000";
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elsif (rising_edge(CLK_I)) then
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else
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if (T2 = '1') then
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case TEMP_state is
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case TEMP_state is
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when TEMP_IDLE =>
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when TEMP_IDLE =>
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TEMP_START <= '0';
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TEMP_START <= '0';
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TEMP_ADDRESS <= "00000000";
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TEMP_ADDRESS <= "00000000";
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TEMP_DATA_IN <= "00000000";
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TEMP_DATA_IN <= "00000000";
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