| Line 18... |
Line 18... |
END testbench;
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END testbench;
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ARCHITECTURE behavior OF testbench IS
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ARCHITECTURE behavior OF testbench IS
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COMPONENT cpu_engine
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COMPONENT cpu_engine
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PORT( CLK : in std_logic;
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PORT(
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CCK : in std_logic;
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clk_i : IN std_logic;
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CLR : in std_logic;
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dat_i : IN std_logic_vector(7 downto 0);
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Q_PC : out std_logic_vector(15 downto 0);
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rst_i : IN std_logic;
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Q_OPC : out std_logic_vector( 7 downto 0);
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ack_i : IN std_logic;
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Q_CAT : out op_category;
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int : IN std_logic;
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Q_IMM : out std_logic_vector(15 downto 0);
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dat_o : OUT std_logic_vector(7 downto 0);
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Q_CYC : out cycle;
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adr_o : OUT std_logic_vector(15 downto 0);
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cyc_o : OUT std_logic;
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-- input/output
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stb_o : OUT std_logic;
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INT : in std_logic;
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tga_o : OUT std_logic_vector(0 to 0);
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IO_ADR : out std_logic_vector(7 downto 0);
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we_o : OUT std_logic;
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IO_RD : out std_logic;
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halt : OUT std_logic;
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IO_WR : out std_logic;
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q_pc : OUT std_logic_vector(15 downto 0);
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IO_RDAT : in std_logic_vector( 7 downto 0);
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q_opc : OUT std_logic_vector(7 downto 0);
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q_cat : OUT op_category;
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-- memory
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q_imm : OUT std_logic_vector(15 downto 0);
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XM_ADR : out std_logic_vector(15 downto 0);
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q_cyc : OUT cycle;
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XM_RDAT : in std_logic_vector( 7 downto 0);
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q_sx : OUT std_logic_vector(1 downto 0);
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XM_WDAT : out std_logic_vector( 7 downto 0);
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q_sy : OUT std_logic_vector(3 downto 0);
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XM_WE : out std_logic;
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q_op : OUT std_logic_vector(4 downto 0);
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XM_CE : out std_logic;
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q_sa : OUT std_logic_vector(4 downto 0);
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q_smq : OUT std_logic;
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-- select signals
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q_we_rr : OUT std_logic;
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Q_SX : out std_logic_vector(1 downto 0);
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q_we_ll : OUT std_logic;
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Q_SY : out std_logic_vector(3 downto 0);
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q_we_sp : OUT SP_OP;
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Q_OP : out std_logic_vector(4 downto 0);
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q_rr : OUT std_logic_vector(15 downto 0);
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Q_SA : out std_logic_vector(4 downto 0);
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q_ll : OUT std_logic_vector(15 downto 0);
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Q_SMQ : out std_logic;
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q_sp : OUT std_logic_vector(15 downto 0)
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-- write enable/select signal
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Q_WE_RR : out std_logic;
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Q_WE_LL : out std_logic;
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Q_WE_SP : out SP_OP;
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Q_RR : out std_logic_vector(15 downto 0);
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Q_LL : out std_logic_vector(15 downto 0);
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Q_SP : out std_logic_vector(15 downto 0);
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HALT : out std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal CLK : std_logic;
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signal CLK_I : std_logic;
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signal CLR : std_logic;
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signal DAT_I : std_logic_vector( 7 downto 0);
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signal Q_PC : std_logic_vector(15 downto 0);
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signal DAT_O : std_logic_vector( 7 downto 0);
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signal Q_OPC : std_logic_vector( 7 downto 0);
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signal RST_I : std_logic;
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signal Q_CAT : op_category;
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signal ACK_I : std_logic;
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signal Q_CYC : cycle;
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signal ADR_O : std_logic_vector(15 downto 0);
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signal Q_IMM : std_logic_vector(15 downto 0);
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signal CYC_O : std_logic;
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signal STB_O : std_logic;
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signal TGA_O : std_logic_vector( 0 downto 0); -- '1' if I/O
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signal WE_O : std_logic;
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signal Q_SP : std_logic_vector(15 downto 0);
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signal Q_LL : std_logic_vector(15 downto 0);
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signal Q_RR : std_logic_vector(15 downto 0);
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|
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-- input/output
|
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signal INT : std_logic;
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signal INT : std_logic;
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signal IO_RD : std_logic;
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signal IO_ADR : std_logic_vector( 7 downto 0);
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signal IO_WR : std_logic;
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signal IO_RDAT : std_logic_vector( 7 downto 0);
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signal HALT : std_logic;
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signal HALT : std_logic;
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-- memory
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-- debug signals
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signal XM_ADR : std_logic_vector(15 downto 0);
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--
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signal XM_RDAT : std_logic_vector( 7 downto 0);
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signal Q_PC : std_logic_vector(15 downto 0);
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signal XM_WDAT : std_logic_vector( 7 downto 0);
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signal Q_OPC : std_logic_vector( 7 downto 0);
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signal XM_WE : std_logic;
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signal Q_CAT : op_category;
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signal XM_CE : std_logic;
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signal Q_IMM : std_logic_vector(15 downto 0);
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signal Q_CYC : cycle;
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|
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-- select signals
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-- select signals
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signal Q_SX : std_logic_vector(1 downto 0);
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signal Q_SX : std_logic_vector(1 downto 0);
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signal Q_SY : std_logic_vector(3 downto 0);
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signal Q_SY : std_logic_vector(3 downto 0);
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signal Q_OP : std_logic_vector(4 downto 0);
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signal Q_OP : std_logic_vector(4 downto 0);
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| Line 99... |
Line 84... |
-- write enable/select signal
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-- write enable/select signal
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signal Q_WE_RR : std_logic;
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signal Q_WE_RR : std_logic;
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signal Q_WE_LL : std_logic;
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signal Q_WE_LL : std_logic;
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signal Q_WE_SP : SP_OP;
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signal Q_WE_SP : SP_OP;
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|
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signal Q_RR : std_logic_vector(15 downto 0);
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signal Q_LL : std_logic_vector(15 downto 0);
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signal Q_SP : std_logic_vector(15 downto 0);
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|
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signal clk_counter : INTEGER := 0;
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signal clk_counter : INTEGER := 0;
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BEGIN
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BEGIN
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|
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uut: cpu_engine PORT MAP(
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uut: cpu_engine
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CLK => CLK,
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PORT MAP(
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CCK => CLK,
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clk_i => clk_i,
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CLR => CLR,
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dat_i => dat_i,
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Q_PC => Q_PC,
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dat_o => dat_o,
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Q_OPC => Q_OPC,
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rst_i => rst_i,
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Q_CAT => Q_CAT,
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ack_i => ack_i,
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Q_IMM => Q_IMM,
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adr_o => adr_o,
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Q_CYC => Q_CYC,
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cyc_o => cyc_o,
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stb_o => stb_o,
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INT => INT,
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tga_o => tga_o,
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IO_ADR => IO_ADR,
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we_o => we_o,
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IO_RD => IO_RD,
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int => int,
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IO_WR => IO_WR,
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halt => halt,
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IO_RDAT => IO_RDAT,
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q_pc => q_pc,
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q_opc => q_opc,
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XM_ADR => XM_ADR,
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q_cat => q_cat,
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XM_RDAT => XM_RDAT,
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q_imm => q_imm,
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XM_WDAT => XM_WDAT,
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q_cyc => q_cyc,
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XM_WE => XM_WE,
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q_sx => q_sx,
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XM_CE => XM_CE,
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q_sy => q_sy,
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q_op => q_op,
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Q_SX => Q_SX,
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q_sa => q_sa,
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Q_SY => Q_SY,
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q_smq => q_smq,
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Q_OP => Q_OP,
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q_we_rr => q_we_rr,
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Q_SA => Q_SA,
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q_we_ll => q_we_ll,
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Q_SMQ => Q_SMQ,
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q_we_sp => q_we_sp,
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q_rr => q_rr,
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Q_WE_RR => Q_WE_RR,
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q_ll => q_ll,
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Q_WE_LL => Q_WE_LL,
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q_sp => q_sp
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Q_WE_SP => Q_WE_SP,
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|
|
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Q_RR => Q_RR,
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Q_LL => Q_LL,
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Q_SP => Q_SP,
|
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HALT => HALT
|
|
);
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);
|
|
|
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ack_i <= stb_o;
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|
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-- *** Test Bench - User Defined Section ***
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-- *** Test Bench - User Defined Section ***
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PROCESS -- clock process for CLK,
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PROCESS -- clock process for CLK_I,
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BEGIN
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BEGIN
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CLOCK_LOOP : LOOP
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CLOCK_LOOP : LOOP
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CLK <= transport '0';
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CLK_I <= transport '0';
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WAIT FOR 1 ns;
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WAIT FOR 1 ns;
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CLK <= transport '1';
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CLK_I <= transport '1';
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WAIT FOR 1 ns;
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WAIT FOR 1 ns;
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WAIT FOR 11 ns;
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WAIT FOR 11 ns;
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CLK <= transport '0';
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CLK_I <= transport '0';
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WAIT FOR 12 ns;
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WAIT FOR 12 ns;
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END LOOP CLOCK_LOOP;
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END LOOP CLOCK_LOOP;
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END PROCESS;
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END PROCESS;
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|
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PROCESS(CLK)
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PROCESS(CLK_I)
|
BEGIN
|
BEGIN
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if (rising_edge(CLK)) then
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if (rising_edge(CLK_I)) then
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if (Q_CYC = M1) then
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if (Q_CYC = M1) then
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CLK_COUNTER <= CLK_COUNTER + 1;
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CLK_COUNTER <= CLK_COUNTER + 1;
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end if;
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end if;
|
|
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if (XM_ADR(0) = '0') then IO_RDAT <= X"44"; -- data
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if (ADR_O(0) = '0') then DAT_I <= X"44"; -- data
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else IO_RDAT <= X"01"; -- control
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else DAT_I <= X"01"; -- control
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end if;
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end if;
|
|
|
case CLK_COUNTER is
|
case CLK_COUNTER is
|
when 0 => CLR <= '1'; INT <= '0';
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when 0 => RST_I <= '1'; INT <= '0';
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when 1 => CLR <= '0';
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when 1 => RST_I <= '0';
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-- when 20 => INT <= '1';
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-- when 20 => INT <= '1';
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|
|
|
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when 1000 => CLK_COUNTER <= 0;
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when 1000 => CLK_COUNTER <= 0;
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ASSERT (FALSE) REPORT
|
ASSERT (FALSE) REPORT
|
