Subversion Repositories c16

--library UNISIM;

--library UNISIM;

--use UNISIM.VComponents.all;

--use UNISIM.VComponents.all;

entity uart_baudgen is

entity uart_baudgen is

        PORT(   CLK_I     : in  std_logic;

        PORT(   CLK_I     : in  std_logic;

                        RD        : in  std_logic;

                        RD        : in  std_logic;

                        WR        : in  std_logic;

                        WR        : in  std_logic;

                        TX_DATA   : in  std_logic_vector(7 downto 0);

                        TX_DATA   : in  std_logic_vector(7 downto 0);

architecture Behavioral of uart_baudgen is

architecture Behavioral of uart_baudgen is

        COMPONENT baudgen

        COMPONENT baudgen

        Generic(bg_clock_freq : integer; bg_baud_rate : integer);

        Generic(bg_clock_freq : integer; bg_baud_rate : integer);

                CE_16 : OUT std_logic

                CE_16 : OUT std_logic

                );

                );

        END COMPONENT;

        END COMPONENT;

        COMPONENT uart

        COMPONENT uart

        PORT(   CLK_I     : in std_logic;

        PORT(   CLK_I     : in std_logic;

                        CE_16     : in std_logic;

                        CE_16     : in std_logic;

                        TX_DATA   : in std_logic_vector(7 downto 0);

                        TX_DATA   : in std_logic_vector(7 downto 0);

                        TX_FLAG   : in  std_logic;

                        TX_FLAG   : in  std_logic;

                        TX_SEROUT : out std_logic;

                        TX_SEROUT : out std_logic;

        baud: baudgen

        baud: baudgen

        GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)

        GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)

        PORT MAP(

        PORT MAP(

                CLK_I => CLK_I,

                CLK_I => CLK_I,

                CE_16 => CE_16

                CE_16 => CE_16

        );

        );

        urt: uart

        urt: uart

        PORT MAP(       CLK_I     => CLK_I,

        PORT MAP(       CLK_I     => CLK_I,

                                CE_16     => CE_16,

                                CE_16     => CE_16,

                                TX_DATA   => LTX_DATA,

                                TX_DATA   => LTX_DATA,

                                TX_FLAG   => TX_FLAG,

                                TX_FLAG   => TX_FLAG,

                                TX_SEROUT => TX_SEROUT,

                                TX_SEROUT => TX_SEROUT,

                                TX_FLAGQ  => TX_FLAGQ,

                                TX_FLAGQ  => TX_FLAGQ,

                        );

                        );

        process(CLK_I)

        process(CLK_I)

        begin

        begin

                if (rising_edge(CLK_I)) then

                if (rising_edge(CLK_I)) then

                                                TX_FLAG <= '0';

                                                TX_FLAG <= '0';

                                                LTX_DATA <= X"33";

                                                LTX_DATA <= X"33";

                                else

                                else

                                        if (RD = '1') then                      -- read Rx data

                                        if (RD = '1') then                      -- read Rx data

                                                LRX_READY    <= '0';

                                                LRX_READY    <= '0';

                                        end if;

                                        end if;

                                        RX_OLD_FLAG <= RX_FLAG;

                                        RX_OLD_FLAG <= RX_FLAG;

                                end if;

                                end if;

                        end if;

                        end if;

        end process;

        end process;

end Behavioral;

end Behavioral;

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