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#=======================================================================
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#=======================================================================
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1: Introduction
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1: Introduction
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---------------
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---------------
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A cellular automata CA) is a discrete model that consists of a grid (1D,
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A cellular automata (CA) is a discrete model that consists of a grid
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2D, 3D ) with objects called cells. Each cell can be in one of a given
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(1D, 2D, 3D ) with objects called cells. Each cell can be in one of a
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set of states (on and off, different colours etc). Each cell has a set
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given finite set of states (on and off, different colours etc). Each
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of cells in close proximity. Given the current internal state of a cell,
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cell has a set of cells in close proximity called neighbours. Given the
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the states of the cells in the close proximity and a given set of update
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current internal state of a cell, the states of the cells in the close
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rules the next state of a cell can be determined. For more information
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proximity and a given set of update rules the next state of a cell can
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about cellular automata, se [1].
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be determined. For more information about cellular automata, se [1].
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The ca_prng IP-core implements a 1D binary cellular automata with wrap
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The ca_prng IP-core implements a 1D binary cellular automata with wrap
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around at the edges (i.e. a ring). The update rules for a given
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around at the edges (i.e. a ring). The update rules for a given
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cell is based on the current state of the cell and the state of its
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cell is based on the current state of the cell and the state of its
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two nearest neighbours (left and right). The cell state for a given cell
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two nearest neighbours (left and right). The cell state for a given cell
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With a three input, binary state the update rule set consists of eight
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With a three input, binary state the update rule set consists of eight
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possible bit updates. In total the ca_prng supports 256 update
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possible bit updates. In total the ca_prng supports 256 update
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rules. For different rules and possible patterns, see [2].
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rules. For different rules and possible patterns, see [2].
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The default update rule used in the ca_prng is rule30. Rule30 is an
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The default update rule used in the ca_prng is rule30. Rule30 is an
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uodate rule that when applied to the CA will produce a class III,
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update rule that when applied to the CA will produce a class III,
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aperiodic, chaotic behaviour. The rule was discovered by Stephen Wolfram
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aperiodic, chaotic behaviour. The rule was discovered by Stephen Wolfram
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[3].
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[3].
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2: IP-core description
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2: IP-core description
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----------------------
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----------------------
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The ca_prng is a CA with 32 cells, implemented as a 32 bit wide
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The ca_prng is a CA with 32 cells, implemented as a 32 bit wide
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register. Each register has separate update logic that looks at the
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register. Each register (cel) has separate update logic that looks at
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current state of the register and its two nearest neighbours (with wrap
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the current state of the register and its two nearest neighbours (with
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around). Register update latency is one cycle.
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wrap around). The total state update latency for all cells is thus one
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cycle.
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The actual update of the registers is controlled by external control
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The actual update of the registers is controlled by external control
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signals that allows a user to set the register initial pattern
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signals that allows a user to set the register initial pattern
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(state) and request generation of new pattern.
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(state) and request generation of new pattern.
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Loading of initial pattern is is accomplished by setting the
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Loading of initial pattern is is accomplished by setting the
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input_patter_data port to the desired inital pattern and then
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input_pattern_data port to the desired inital pattern and then
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asserting the load_input_pattern port for one clock cycle.
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asserting the load_input_pattern port for one clock cycle.
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Requesting a new pattern is accomplished by asserting the next_pattern
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Requesting a new pattern is accomplished by asserting the next_pattern
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port.
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port.
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internal registers are equipped with a synhronous, active low reset.
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internal registers are equipped with a synhronous, active low reset.
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3: IP-core delivery contents
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3: IP-core delivery contents
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----------------------------
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----------------------------
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The ca_prng is provided as RTL source code written in Verilog 2001
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The ca_prng core is provided as RTL source code written in Verilog 2001
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compliant code. The ca_prng delivery also contains a testbench that
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compliant code. The ca_prng delivery also contains a testbench that
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verifies the functionality. Finally the core contains a functional model
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verifies the functionality. Finally the core contains a functional model
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written in Python as well as documentation (this file).
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written in Python as well as documentation (this file).
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The provided testbench has been used to verify the core using the
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The provided testbench has been used to verify the core using the
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ModelSim as well as the Icarus Verilog simulators.
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ModelSim as well as the Icarus Verilog simulators.
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The ca_prng core has been implemented in FPGA tools from Altera and
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The ca_prng core has been implemented in FPGA tools from Altera and
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Xilinx. The following table lists the area and speed achieved.
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Xilinx. The following table lists the area and speed achieved for the
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ca_prng core as a stand alone core.
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Altera Devices (implemented using Quartus 9.0)
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Altera Devices (implemented using Quartus 9.0)
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Stratix II
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Stratix II
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---------
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---------
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Device: EP2S15
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Device: EP2S15
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