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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
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-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
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--
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--
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-- Create Date: 02/01/2008
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-- Create Date: 02/01/2008
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-- Last Update: 03/06/2008
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-- Last Update: 03/28/2008
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-- Project Name: camellia-vhdl
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-- Project Name: camellia-vhdl
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-- Description: Looping version of Camellia
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-- Description: Looping version of Camellia
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--
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--
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-- Copyright (C) 2008 Paolo Fulgoni
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-- Copyright (C) 2008 Paolo Fulgoni
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-- This file is part of camellia-vhdl.
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-- This file is part of camellia-vhdl.
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entity camellia is
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entity camellia is
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port (
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port (
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR (0 to 127);
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data_in : in STD_LOGIC_VECTOR (0 to 127);
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enc_dec : in STD_LOGIC;
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data_rdy : in STD_LOGIC;
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data_acq : out STD_LOGIC;
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key : in STD_LOGIC_VECTOR (0 to 255);
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key : in STD_LOGIC_VECTOR (0 to 255);
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k_len : in STD_LOGIC_VECTOR (0 to 1);
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k_len : in STD_LOGIC_VECTOR (0 to 1);
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new_key : in STD_LOGIC;
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key_rdy : in STD_LOGIC;
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enc_dec : in STD_LOGIC;
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key_acq : out STD_LOGIC;
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input_rdy : in STD_LOGIC;
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data_out : out STD_LOGIC_VECTOR (0 to 127)
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data_out : out STD_LOGIC_VECTOR (0 to 127);
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output_rdy : out STD_LOGIC
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);
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);
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end camellia;
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end camellia;
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architecture RTL of camellia is
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architecture RTL of camellia is
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signal s_clk : STD_LOGIC;
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signal s_clk : STD_LOGIC;
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signal s_reset : STD_LOGIC;
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signal s_reset : STD_LOGIC;
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signal s_data_in : STD_LOGIC_VECTOR (0 to 127);
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signal s_data_in : STD_LOGIC_VECTOR (0 to 127);
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signal s_enc_dec : STD_LOGIC;
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signal s_data_rdy : STD_LOGIC;
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signal s_data_acq : STD_LOGIC;
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signal s_key_in : STD_LOGIC_VECTOR (0 to 255);
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signal s_key_in : STD_LOGIC_VECTOR (0 to 255);
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signal s_k_len : STD_LOGIC_VECTOR (0 to 1);
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signal s_k_len : STD_LOGIC_VECTOR (0 to 1);
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signal s_new_key : STD_LOGIC;
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signal s_key_rdy : STD_LOGIC;
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signal s_enc_dec : STD_LOGIC;
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signal s_key_acq : STD_LOGIC;
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signal s_input_rdy : STD_LOGIC;
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signal s_nxt_input : STD_LOGIC;
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signal s_data_to : STD_LOGIC_VECTOR (0 to 127);
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signal s_data_to : STD_LOGIC_VECTOR (0 to 127);
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signal s_output_rdy : STD_LOGIC;
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signal s_k1 : STD_LOGIC_VECTOR (0 to 63);
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signal s_k1 : STD_LOGIC_VECTOR (0 to 63);
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signal s_k2 : STD_LOGIC_VECTOR (0 to 63);
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signal s_k2 : STD_LOGIC_VECTOR (0 to 63);
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signal s_newdata : STD_LOGIC;
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signal s_newdata : STD_LOGIC;
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signal s_sel : STD_LOGIC;
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signal s_sel : STD_LOGIC;
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signal s_pre_xor : STD_LOGIC_VECTOR (0 to 127);
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signal s_pre_xor : STD_LOGIC_VECTOR (0 to 127);
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Line 87... |
component control is
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component control is
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port (
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port (
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR (0 to 127);
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data_in : in STD_LOGIC_VECTOR (0 to 127);
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enc_dec : in STD_LOGIC;
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data_rdy : in STD_LOGIC;
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data_acq : out STD_LOGIC;
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key_in : in STD_LOGIC_VECTOR (0 to 255);
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key_in : in STD_LOGIC_VECTOR (0 to 255);
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k_len : in STD_LOGIC_VECTOR (0 to 1);
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k_len : in STD_LOGIC_VECTOR (0 to 1);
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new_key : in STD_LOGIC;
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key_rdy : in STD_LOGIC;
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enc_dec : in STD_LOGIC;
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key_acq : out STD_LOGIC;
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input_rdy : in STD_LOGIC;
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data_to : out STD_LOGIC_VECTOR (0 to 127);
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data_to : out STD_LOGIC_VECTOR (0 to 127);
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output_rdy : out STD_LOGIC;
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k1 : out STD_LOGIC_VECTOR (0 to 63);
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k1 : out STD_LOGIC_VECTOR (0 to 63);
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k2 : out STD_LOGIC_VECTOR (0 to 63);
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k2 : out STD_LOGIC_VECTOR (0 to 63);
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newdata : out STD_LOGIC;
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newdata : out STD_LOGIC;
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sel : out STD_LOGIC;
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sel : out STD_LOGIC;
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pre_xor : out STD_LOGIC_VECTOR (0 to 127);
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pre_xor : out STD_LOGIC_VECTOR (0 to 127);
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CTRL : control
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CTRL : control
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port map(
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port map(
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clk => s_clk,
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clk => s_clk,
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reset => s_reset,
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reset => s_reset,
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data_in => s_data_in,
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data_in => s_data_in,
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enc_dec => s_enc_dec,
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data_rdy => s_data_rdy,
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data_acq => s_data_acq,
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key_in => s_key_in,
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key_in => s_key_in,
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k_len => s_k_len,
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k_len => s_k_len,
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new_key => s_new_key,
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key_rdy => s_key_rdy,
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enc_dec => s_enc_dec,
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key_acq => s_key_acq,
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input_rdy => s_input_rdy,
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data_to => s_data_to,
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data_to => s_data_to,
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output_rdy => s_output_rdy,
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k1 => s_k1,
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k1 => s_k1,
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k2 => s_k2,
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k2 => s_k2,
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newdata => s_newdata,
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newdata => s_newdata,
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sel => s_sel,
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sel => s_sel,
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pre_xor => s_pre_xor,
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pre_xor => s_pre_xor,
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Line 148... |
);
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);
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s_clk <= clk;
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s_clk <= clk;
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s_reset <= reset;
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s_reset <= reset;
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s_data_in <= data_in;
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s_data_in <= data_in;
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s_enc_dec <= enc_dec;
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s_data_rdy <= data_rdy;
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s_key_in <= key;
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s_key_in <= key;
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s_k_len <= k_len;
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s_k_len <= k_len;
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s_new_key <= new_key;
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s_key_rdy <= key_rdy;
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s_enc_dec <= enc_dec;
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s_input_rdy <= input_rdy;
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data_acq <= s_data_acq;
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key_acq <= s_key_acq;
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data_out <= s_data_from(64 to 127) & s_data_from(0 to 63);
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data_out <= s_data_from(64 to 127) & s_data_from(0 to 63);
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output_rdy <= s_output_rdy;
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end RTL;
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end RTL;
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No newline at end of file
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No newline at end of file
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