| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.26 2003/09/25 18:55:49 mohor
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// Synchronization changed, error counters fixed.
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//
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// Revision 1.25 2003/07/16 13:40:35 mohor
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// Revision 1.25 2003/07/16 13:40:35 mohor
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// Fixed according to the linter.
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// Fixed according to the linter.
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//
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//
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// Revision 1.24 2003/07/10 15:32:28 mohor
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// Revision 1.24 2003/07/10 15:32:28 mohor
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// Unused signal removed.
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// Unused signal removed.
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| Line 162... |
Line 165... |
tx_point,
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tx_point,
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hard_sync,
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hard_sync,
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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rx_idle,
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rx_idle,
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not_first_bit_of_inter,
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rx_inter,
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transmitting,
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transmitting,
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transmitter,
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transmitter,
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go_rx_inter,
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go_rx_inter,
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tx_next,
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tx_next,
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| Line 194... |
Line 197... |
input [2:0] time_segment2;
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input [2:0] time_segment2;
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input triple_sampling;
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input triple_sampling;
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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input rx_idle;
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input rx_idle;
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input not_first_bit_of_inter;
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input rx_inter;
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input transmitting;
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input transmitting;
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input transmitter;
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input transmitter;
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input go_rx_inter;
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input go_rx_inter;
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input tx_next;
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input tx_next;
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| Line 243... |
Line 246... |
wire resync;
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wire resync;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = (rx_idle | not_first_bit_of_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
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assign hard_sync = (rx_idle | rx_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
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assign resync = (~rx_idle) & (~not_first_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
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assign resync = (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
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/* Generating general enable signal that defines baud rate. */
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/* Generating general enable signal that defines baud rate. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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| Line 450... |
Line 453... |
/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
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/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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hard_sync_blocked <=#Tp 1'b0;
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hard_sync_blocked <=#Tp 1'b0;
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else if (hard_sync & clk_en_q | transmitting & transmitter & tx_point)
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// else if (hard_sync & clk_en_q | transmitting & transmitter & tx_point)
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else if (hard_sync & clk_en_q | transmitting & transmitter & tx_point & (~tx_next))
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hard_sync_blocked <=#Tp 1'b1;
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hard_sync_blocked <=#Tp 1'b1;
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// else if (go_rx_inter)
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// else if (go_rx_inter)
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else if (go_rx_inter | (rx_idle | not_first_bit_of_inter) & sample_point & sampled_bit) // When a glitch performed synchronization
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else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization
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hard_sync_blocked <=#Tp 1'b0;
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hard_sync_blocked <=#Tp 1'b0;
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end
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end
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