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Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.24 2003/07/10 15:32:28 mohor
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// Unused signal removed.
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//
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// Revision 1.23 2003/07/10 01:59:04 tadejm
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// Revision 1.23 2003/07/10 01:59:04 tadejm
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// Synchronization fixed. In some strange cases it didn't work according to
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// Synchronization fixed. In some strange cases it didn't work according to
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// the VHDL reference model.
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// the VHDL reference model.
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//
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//
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// Revision 1.22 2003/07/07 11:21:37 mohor
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// Revision 1.22 2003/07/07 11:21:37 mohor
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| Line 197... |
Line 200... |
reg clk_en_q;
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reg clk_en_q;
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reg sync_blocked;
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reg sync_blocked;
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reg hard_sync_blocked;
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reg hard_sync_blocked;
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reg sampled_bit;
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reg sampled_bit;
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reg sampled_bit_q;
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reg sampled_bit_q;
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reg [4:0] quant_cnt;
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reg [3:0] quant_cnt;
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reg [3:0] delay;
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reg [3:0] delay;
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reg sync;
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reg sync;
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reg seg1;
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reg seg1;
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reg seg2;
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reg seg2;
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reg resync_latched;
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reg resync_latched;
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| Line 213... |
Line 216... |
reg tx_point;
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reg tx_point;
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wire go_sync_unregistered;
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wire go_sync_unregistered;
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wire go_seg1_unregistered;
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wire go_seg1_unregistered;
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wire go_seg2_unregistered;
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wire go_seg2_unregistered;
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wire [8:0] preset_cnt;
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wire [7:0] preset_cnt;
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wire sync_window;
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wire sync_window;
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wire resync;
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wire resync;
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wire quant_cnt_rst;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = (rx_idle | not_first_bit_of_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
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assign hard_sync = (rx_idle | not_first_bit_of_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
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| Line 229... |
Line 231... |
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/* Generating general enable signal that defines baud rate. */
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/* Generating general enable signal that defines baud rate. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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clk_cnt <= 0;
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clk_cnt <= 7'h0;
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else if (clk_cnt >= (preset_cnt-1'b1))
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else if (clk_cnt >= (preset_cnt-1'b1))
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clk_cnt <=#Tp 0;
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clk_cnt <=#Tp 7'h0;
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else
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else
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clk_cnt <=#Tp clk_cnt + 1'b1;
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clk_cnt <=#Tp clk_cnt + 1'b1;
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end
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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clk_en <= 1'b0;
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clk_en <= 1'b0;
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else if (clk_cnt == (preset_cnt-1'b1))
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else if ({1'b0, clk_cnt} == (preset_cnt-1'b1))
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clk_en <=#Tp 1'b1;
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clk_en <=#Tp 1'b1;
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else
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else
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clk_en <=#Tp 1'b0;
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clk_en <=#Tp 1'b0;
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end
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end
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| Line 268... |
Line 270... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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go_sync <= 1'b0;
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go_sync <=#Tp 1'b0;
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else
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else
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go_sync <=#Tp go_sync_unregistered;
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go_sync <=#Tp go_sync_unregistered;
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end
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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go_seg1 <= 1'b0;
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go_seg1 <=#Tp 1'b0;
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else
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else
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go_seg1 <=#Tp go_seg1_unregistered;
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go_seg1 <=#Tp go_seg1_unregistered;
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end
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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go_seg2 <= 1'b0;
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go_seg2 <=#Tp 1'b0;
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else
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else
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go_seg2 <=#Tp go_seg2_unregistered;
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go_seg2 <=#Tp go_seg2_unregistered;
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end
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end
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| Line 319... |
Line 321... |
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/* Synchronization stage/segment */
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/* Synchronization stage/segment */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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sync <= 0;
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sync <= 1'b0;
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else if (go_sync)
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else if (go_sync)
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sync <=#Tp 1'b1;
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sync <=#Tp 1'b1;
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else if (clk_en_q | go_seg1)
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else if (clk_en_q | go_seg1)
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sync <=#Tp 1'b0;
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sync <=#Tp 1'b0;
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end
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end
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| Line 331... |
Line 333... |
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/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
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/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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seg1 <= 1;
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seg1 <= 1'b1;
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else if (go_seg1)
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else if (go_seg1)
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seg1 <=#Tp 1'b1;
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seg1 <=#Tp 1'b1;
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else if (go_seg2)
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else if (go_seg2)
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seg1 <=#Tp 1'b0;
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seg1 <=#Tp 1'b0;
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end
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end
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| Line 343... |
Line 345... |
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/* Seg2 stage/segment */
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/* Seg2 stage/segment */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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seg2 <= 0;
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seg2 <= 1'b0;
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else if (go_seg2)
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else if (go_seg2)
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seg2 <=#Tp 1'b1;
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seg2 <=#Tp 1'b1;
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else if (go_sync | go_seg1)
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else if (go_sync | go_seg1)
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seg2 <=#Tp 1'b0;
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seg2 <=#Tp 1'b0;
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end
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end
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/* Quant counter */
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/* Quant counter */
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assign quant_cnt_rst = go_sync | go_seg1 | go_seg2;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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quant_cnt <= 0;
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quant_cnt <= 4'h0;
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else if (quant_cnt_rst)
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else if (go_sync | go_seg1 | go_seg2)
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quant_cnt <=#Tp 0;
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quant_cnt <=#Tp 4'h0;
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else if (clk_en_q)
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else if (clk_en_q)
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quant_cnt <=#Tp quant_cnt + 1'b1;
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quant_cnt <=#Tp quant_cnt + 1'b1;
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end
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end
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/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
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/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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delay <= 0;
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delay <= 4'h0;
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else if (resync & seg1 & (~transmitting)) // when transmitting 0 with positive error delay is set to 0
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else if (resync & seg1 & (~transmitting)) // when transmitting 0 with positive error delay is set to 0
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delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
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delay <=#Tp (quant_cnt > {2'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);
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else if (go_sync | go_seg1)
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else if (go_sync | go_seg1)
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delay <=#Tp 0;
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delay <=#Tp 4'h0;
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end
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end
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// If early edge appears within this window (in seg2 stage), phase error is fully compensated
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// If early edge appears within this window (in seg2 stage), phase error is fully compensated
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assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
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assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
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Line 396... |
// When enabled, tripple sampling is done here.
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// When enabled, tripple sampling is done here.
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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sampled_bit <= 1;
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sampled_bit <= 1'b1;
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sampled_bit_q <= 1;
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sampled_bit_q <= 1'b1;
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sample_point <= 0;
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sample_point <= 1'b0;
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end
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end
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else if (clk_en_q & (~hard_sync))
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else if (clk_en_q & (~hard_sync))
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begin
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begin
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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begin
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begin
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sample_point <=#Tp 1;
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sample_point <=#Tp 1'b1;
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sampled_bit_q <=#Tp sampled_bit;
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sampled_bit_q <=#Tp sampled_bit;
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if (triple_sampling)
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if (triple_sampling)
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sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
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sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
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else
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else
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sampled_bit <=#Tp rx;
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sampled_bit <=#Tp rx;
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end
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end
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end
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end
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else
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else
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sample_point <=#Tp 0;
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sample_point <=#Tp 1'b0;
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end
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end
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/* Blocking synchronization (can occur only once in a bit time) */
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/* Blocking synchronization (can occur only once in a bit time) */
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| Line 428... |
Line 428... |
sync_blocked <=#Tp 1'b1;
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sync_blocked <=#Tp 1'b1;
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else if (clk_en_q)
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else if (clk_en_q)
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begin
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begin
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if (resync)
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if (resync)
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sync_blocked <=#Tp 1'b1;
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sync_blocked <=#Tp 1'b1;
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// else if (seg2 & (quant_cnt[2:0] == time_segment2))
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else if (go_seg2)
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else if (go_seg2)
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sync_blocked <=#Tp 1'b0;
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sync_blocked <=#Tp 1'b0;
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end
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end
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end
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end
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