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Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2003/02/19 14:44:03 mohor
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// CAN core finished. Host interface added. Registers finished.
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// Synchronization to the wishbone finished.
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//
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// Revision 1.11 2003/02/14 20:17:01 mohor
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// Revision 1.11 2003/02/14 20:17:01 mohor
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// Several registers added. Not finished, yet.
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// Several registers added. Not finished, yet.
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//
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//
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// Revision 1.10 2003/02/11 00:56:06 mohor
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// Revision 1.10 2003/02/11 00:56:06 mohor
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// Wishbone interface added.
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// Wishbone interface added.
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| Line 104... |
Line 108... |
wr,
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wr,
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data_in,
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data_in,
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addr,
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addr,
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data_out,
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data_out,
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fifo_selected,
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reset_mode,
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reset_mode,
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release_buffer,
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release_buffer,
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extended_mode,
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extended_mode,
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overrun,
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overrun,
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| Line 124... |
Line 129... |
input [7:0] data_in;
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input [7:0] data_in;
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input [7:0] addr;
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input [7:0] addr;
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input reset_mode;
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input reset_mode;
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input release_buffer;
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input release_buffer;
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input extended_mode;
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input extended_mode;
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input fifo_selected;
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output [7:0] data_out;
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output [7:0] data_out;
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output overrun;
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output overrun;
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output info_empty;
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output info_empty;
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output [6:0] info_cnt;
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output [6:0] info_cnt;
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`ifdef ACTEL_APA_RAM
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`else
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reg [7:0] fifo [0:63];
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reg [7:0] fifo [0:63];
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reg [3:0] length_fifo[0:63];
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reg overrun_info[0:63];
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`endif
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reg [5:0] rd_pointer;
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reg [5:0] rd_pointer;
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reg [5:0] wr_pointer;
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reg [5:0] wr_pointer;
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reg [5:0] read_address;
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reg [5:0] read_address;
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reg [3:0] length_info[0:63];
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reg [5:0] wr_info_pointer;
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reg [5:0] wr_info_pointer;
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reg [5:0] rd_info_pointer;
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reg [5:0] rd_info_pointer;
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reg overrun_info[0:63];
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reg wr_q;
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reg wr_q;
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reg [3:0] len_cnt;
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reg [3:0] len_cnt;
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reg [6:0] fifo_cnt;
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reg [6:0] fifo_cnt;
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reg [6:0] info_cnt;
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reg [6:0] info_cnt;
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reg latch_overrun;
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reg latch_overrun;
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wire [3:0] length_info;
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wire write_length_info;
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wire write_length_info;
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wire fifo_empty;
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wire fifo_empty;
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wire fifo_full;
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wire fifo_full;
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wire info_full;
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wire info_full;
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Line 198... |
else if (write_length_info & (~info_full))
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else if (write_length_info & (~info_full))
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wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
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wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
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end
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end
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// length_info
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always @ (posedge clk)
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begin
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if (write_length_info & (~info_full))
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length_info[wr_info_pointer] <=#Tp len_cnt;
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end
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// overrun_info
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always @ (posedge clk)
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begin
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if (write_length_info & (~info_full))
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overrun_info[wr_info_pointer] <=#Tp latch_overrun | (wr & fifo_full);
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end
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// reading overrun
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assign overrun = overrun_info[rd_info_pointer];
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// rd_info_pointer
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// rd_info_pointer
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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| Line 225... |
Line 217... |
always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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rd_pointer <= 0;
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rd_pointer <= 0;
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else if (release_buffer & (~fifo_empty))
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else if (release_buffer & (~fifo_empty))
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rd_pointer <=#Tp rd_pointer + length_info[rd_info_pointer];
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rd_pointer <=#Tp rd_pointer + length_info;
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else if (reset_mode)
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else if (reset_mode)
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rd_pointer <=#Tp 0;
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rd_pointer <=#Tp 0;
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end
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end
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Line 255... |
if (rst)
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if (rst)
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fifo_cnt <= 0;
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fifo_cnt <= 0;
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else if (wr & (~release_buffer) & (~fifo_full))
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else if (wr & (~release_buffer) & (~fifo_full))
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fifo_cnt <=#Tp fifo_cnt + 1'b1;
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fifo_cnt <=#Tp fifo_cnt + 1'b1;
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else if ((~wr) & release_buffer & (~fifo_empty))
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else if ((~wr) & release_buffer & (~fifo_empty))
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fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer];
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fifo_cnt <=#Tp fifo_cnt - length_info;
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else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
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else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
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fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer] + 1'b1;
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fifo_cnt <=#Tp fifo_cnt - length_info + 1'b1;
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else if (reset_mode)
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else if (reset_mode)
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fifo_cnt <=#Tp 0;
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fifo_cnt <=#Tp 0;
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end
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end
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assign fifo_full = fifo_cnt == 64;
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assign fifo_full = fifo_cnt == 64;
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assign fifo_empty = fifo_cnt == 0;
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assign fifo_empty = fifo_cnt == 0;
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// Counting data in length_info and overrun_info fifo
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// Counting data in length_fifo and overrun_info fifo
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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info_cnt <= 0;
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info_cnt <= 0;
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else if (write_length_info ^ release_buffer)
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else if (write_length_info ^ release_buffer)
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| Line 292... |
Line 284... |
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assign info_full = info_cnt == 64;
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assign info_full = info_cnt == 64;
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assign info_empty = info_cnt == 0;
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assign info_empty = info_cnt == 0;
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// writing data to fifo
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always @ (posedge clk)
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begin
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if (wr & (~fifo_full))
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fifo[wr_pointer] <=#Tp data_in;
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end
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// Selecting which address will be used for reading data from rx fifo
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// Selecting which address will be used for reading data from rx fifo
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always @ (extended_mode or rd_pointer or addr)
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always @ (extended_mode or rd_pointer or addr)
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begin
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begin
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if (extended_mode) // extended mode
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if (extended_mode) // extended mode
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begin
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begin
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Line 299... |
end
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end
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end
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end
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`ifdef ACTEL_APA_RAM
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actel_ram_64x8_sync fifo
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(
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.DO (data_out),
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.RCLOCK (clk),
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.WCLOCK (clk),
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.DI (data_in),
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.PO (), // parity not used
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.WRB (~(wr & (~fifo_full))),
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.RDB (~fifo_selected),
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.WADDR (wr_pointer),
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.RADDR (read_address)
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);
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actel_ram_64x4_sync info_fifo
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(
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.DO (length_info),
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.RCLOCK (clk),
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.WCLOCK (clk),
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.DI (len_cnt),
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.PO (), // parity not used
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.WRB (~(write_length_info & (~info_full))),
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.RDB (1'b0), // always enabled
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.WADDR (wr_info_pointer),
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.RADDR (rd_info_pointer)
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);
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actel_ram_64x1_sync overrun_fifo
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(
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.DO (overrun),
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.RCLOCK (clk),
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.WCLOCK (clk),
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.DI (latch_overrun | (wr & fifo_full)),
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.PO (), // parity not used
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.WRB (~(write_length_info & (~info_full))),
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.RDB (1'b0), // always enabled
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.WADDR (wr_info_pointer),
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.RADDR (rd_info_pointer)
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);
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`else
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// writing data to fifo
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always @ (posedge clk)
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begin
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if (wr & (~fifo_full))
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fifo[wr_pointer] <=#Tp data_in;
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end
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// reading from fifo
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assign data_out = fifo[read_address];
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assign data_out = fifo[read_address];
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// writing length_fifo
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always @ (posedge clk)
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begin
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if (write_length_info & (~info_full))
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length_fifo[wr_info_pointer] <=#Tp len_cnt;
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end
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// reading length_fifo
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assign length_info = length_fifo[rd_info_pointer];
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// overrun_info
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always @ (posedge clk)
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begin
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if (write_length_info & (~info_full))
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overrun_info[wr_info_pointer] <=#Tp latch_overrun | (wr & fifo_full);
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end
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// reading overrun
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assign overrun = overrun_info[rd_info_pointer];
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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