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[/] [can/] [tags/] [asyst_3/] [rtl/] [verilog/] [can_fifo.v] - Diff between revs 48 and 51

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Rev 48 Rev 51
Line 48... Line 48... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.13  2003/03/01 22:53:33  mohor
 
 
 
// Actel APA ram supported.
 
 
 
//
 
// Revision 1.12  2003/02/19 14:44:03  mohor
 
// Revision 1.12  2003/02/19 14:44:03  mohor
 
// CAN core finished. Host interface added. Registers finished.
 
// CAN core finished. Host interface added. Registers finished.
 
// Synchronization to the wishbone finished.
 
// Synchronization to the wishbone finished.
 
//
 
//
 
// Revision 1.11  2003/02/14 20:17:01  mohor
 
// Revision 1.11  2003/02/14 20:17:01  mohor
Line 138... Line 141... 
output        info_empty;
 
output        info_empty;
 
output  [6:0] info_cnt;
 
output  [6:0] info_cnt;
 
 
 
 
 
`ifdef ACTEL_APA_RAM
 
`ifdef ACTEL_APA_RAM
 
`else
 
`else
 
 
 
`ifdef XILINX_RAM
 
 
 
`else
 
  reg     [7:0] fifo [0:63];
 
  reg     [7:0] fifo [0:63];
 
  reg     [3:0] length_fifo[0:63];
 
  reg     [3:0] length_fifo[0:63];
 
  reg           overrun_info[0:63];
 
  reg           overrun_info[0:63];
 
`endif
 
`endif
 
 
 
`endif
 
 
 
 
 
reg     [5:0] rd_pointer;
 
reg     [5:0] rd_pointer;
 
reg     [5:0] wr_pointer;
 
reg     [5:0] wr_pointer;
 
reg     [5:0] read_address;
 
reg     [5:0] read_address;
 
reg     [5:0] wr_info_pointer;
 
reg     [5:0] wr_info_pointer;
Line 341... Line 347... 
    .RDB     (1'b0),                   // always enabled
 
    .RDB     (1'b0),                   // always enabled
 
    .WADDR   (wr_info_pointer),
 
    .WADDR   (wr_info_pointer),
 
    .RADDR   (rd_info_pointer)
 
    .RADDR   (rd_info_pointer)
 
  );
 
  );
 
`else
 
`else
 
 
 
`ifdef XILINX_RAM
 
 
 
 
 
 
 
/*
 
 
 
  ram_64x8_sync fifo
 
 
 
  (
 
 
 
    .addra(wr_pointer),
 
 
 
    .addrb(read_address),
 
 
 
    .clka(clk),
 
 
 
    .clkb(clk),
 
 
 
    .dina(data_in),
 
 
 
    .doutb(data_out),
 
 
 
    .wea(wr & (~fifo_full))
 
 
 
  );
 
 
 
*/
 
 
 
 
 
 
 
  RAMB4_S8_S8 fifo
 
 
 
  (
 
 
 
    .DOA(),
 
 
 
    .DOB(data_out),
 
 
 
    .ADDRA({3'h0, wr_pointer}),
 
 
 
    .CLKA(clk),
 
 
 
    .DIA(data_in),
 
 
 
    .ENA(1'b1),
 
 
 
    .RSTA(1'b0),
 
 
 
    .WEA(wr & (~fifo_full)),
 
 
 
    .ADDRB({3'h0, read_address}),
 
 
 
    .CLKB(clk),
 
 
 
    .DIB(8'h0),
 
 
 
    .ENB(1'b1),
 
 
 
    .RSTB(1'b0),
 
 
 
    .WEB(1'b0)
 
 
 
  );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/*
 
 
 
  ram_64x4_sync info_fifo
 
 
 
  (
 
 
 
    .addra(wr_info_pointer),
 
 
 
    .addrb(rd_info_pointer),
 
 
 
    .clka(clk),
 
 
 
    .clkb(clk),
 
 
 
    .dina(len_cnt),
 
 
 
    .doutb(length_info),
 
 
 
    .wea(write_length_info & (~info_full))
 
 
 
  );
 
 
 
*/
 
 
 
  RAMB4_S4_S4 info_fifo
 
 
 
  (
 
 
 
    .DOA(),
 
 
 
    .DOB(length_info),
 
 
 
    .ADDRA({4'h0, wr_info_pointer}),
 
 
 
    .CLKA(clk),
 
 
 
    .DIA(len_cnt),
 
 
 
    .ENA(1'b1),
 
 
 
    .RSTA(1'b0),
 
 
 
    .WEA(write_length_info & (~info_full)),
 
 
 
    .ADDRB({4'h0, rd_info_pointer}),
 
 
 
    .CLKB(clk),
 
 
 
    .DIB(4'h0),
 
 
 
    .ENB(1'b1),
 
 
 
    .RSTB(1'b0),
 
 
 
    .WEB(1'b0)
 
 
 
  );
 
 
 
 
 
 
 
/*
 
 
 
  ram_64x1_sync overrun_fifo
 
 
 
  (
 
 
 
    .addra(wr_info_pointer),
 
 
 
    .addrb(rd_info_pointer),
 
 
 
    .clka(clk),
 
 
 
    .clkb(clk),
 
 
 
    .dina(latch_overrun | (wr & fifo_full)),
 
 
 
    .doutb(overrun),
 
 
 
    .wea(write_length_info & (~info_full))
 
 
 
  );
 
 
 
*/
 
 
 
 
 
 
 
 
 
 
 
  RAMB4_S1_S1 overrun_fifo
 
 
 
  (
 
 
 
    .DOA(),
 
 
 
    .DOB(overrun),
 
 
 
    .ADDRA({6'h0, wr_info_pointer}),
 
 
 
    .CLKA(clk),
 
 
 
    .DIA(latch_overrun | (wr & fifo_full)),
 
 
 
    .ENA(1'b1),
 
 
 
    .RSTA(1'b0),
 
 
 
    .WEA(write_length_info & (~info_full)),
 
 
 
    .ADDRB({6'h0, rd_info_pointer}),
 
 
 
    .CLKB(clk),
 
 
 
    .DIB(1'h0),
 
 
 
    .ENB(1'b1),
 
 
 
    .RSTB(1'b0),
 
 
 
    .WEB(1'b0)
 
 
 
  );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
`else
 
  // writing data to fifo
 
  // writing data to fifo
 
  always @ (posedge clk)
 
  always @ (posedge clk)
 
  begin
 
  begin
 
    if (wr & (~fifo_full))
 
    if (wr & (~fifo_full))
 
      fifo[wr_pointer] <=#Tp data_in;
 
      fifo[wr_pointer] <=#Tp data_in;
Line 375... Line 482... 
  // reading overrun
 
  // reading overrun
 
  assign overrun = overrun_info[rd_info_pointer];
 
  assign overrun = overrun_info[rd_info_pointer];
 
 
 
 
 
 
 
 
 
`endif
 
`endif
 
 
 
`endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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