URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [complete_1/] [syn/] [synplicity/] [can.prj] - Diff between revs 48 and 49

Rev 48	Rev 49
Line 4...	Line 4...
`#-- Written on Sat Mar 1 21:07:14 2003`	`#-- Written on Sat Mar 1 21:07:14 2003`


`#add_file options`	`#add_file options`
`add_file -verilog "$LIB/proasic/proasicplus.v"`	`add_file -verilog "$LIB/proasic/proasicplus.v"`
`add_file -verilog "../../../memory/actel/ram_64x8_sync_async/actel_ram_64x8_sync_async.v"`	`add_file -verilog "../../../memory/actel/ram_64x8_sync/actel_ram_64x8_sync.v"`
`add_file -verilog "../../../memory/actel/ram_64x4_sync_async/actel_ram_64x4_sync_async.v"`	`add_file -verilog "../../../memory/actel/ram_64x4_sync/actel_ram_64x4_sync.v"`
`add_file -verilog "../../../memory/actel/ram_64x1_sync_async/actel_ram_64x1_sync_async.v"`	`add_file -verilog "../../../memory/actel/ram_64x1_sync/actel_ram_64x1_sync.v"`
`add_file -verilog "../../rtl/verilog/can_registers.v"`	`add_file -verilog "../../rtl/verilog/can_registers.v"`
`add_file -verilog "../../rtl/verilog/can_bsp.v"`	`add_file -verilog "../../rtl/verilog/can_bsp.v"`
`add_file -verilog "../../rtl/verilog/can_btl.v"`	`add_file -verilog "../../rtl/verilog/can_btl.v"`
`add_file -verilog "../../rtl/verilog/can_defines.v"`	`add_file -verilog "../../rtl/verilog/can_defines.v"`
`add_file -verilog "../../rtl/verilog/can_register.v"`	`add_file -verilog "../../rtl/verilog/can_register.v"`