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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/12/27 00:12:52 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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//
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// Revision 1.4 2002/12/26 01:33:05 mohor
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// Revision 1.4 2002/12/26 01:33:05 mohor
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// Tripple sampling supported.
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// Tripple sampling supported.
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//
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//
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// Revision 1.3 2002/12/25 23:44:16 mohor
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// Revision 1.3 2002/12/25 23:44:16 mohor
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// Commented lines removed.
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// Commented lines removed.
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| Line 70... |
Line 73... |
clk,
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clk,
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rst,
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rst,
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rx,
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rx,
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/* Mode register */
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/* Mode register */
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reset_mode, // Not used !!!
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reset_mode,
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/* Bus Timing 0 register */
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/* Bus Timing 0 register */
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baud_r_presc,
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baud_r_presc,
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sync_jump_width,
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sync_jump_width,
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Line 85... |
time_segment1,
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time_segment1,
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time_segment2,
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time_segment2,
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triple_sampling,
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triple_sampling,
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/* Output signals from this module */
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/* Output signals from this module */
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take_sample,
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clk_en,
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clk_en,
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sample_point,
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sampled_bit,
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sampled_bit_q,
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/* Output from can_bsp module */
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rx_idle
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/* States */
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idle
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);
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);
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Line 116... |
/* Bus Timing 1 register */
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/* Bus Timing 1 register */
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input [3:0] time_segment1;
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input [3:0] time_segment1;
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input [2:0] time_segment2;
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input [2:0] time_segment2;
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input triple_sampling;
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input triple_sampling;
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/* Output from can_bsp module */
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input rx_idle;
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/* Output signals from this module */
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/* Output signals from this module */
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output take_sample; // NOT USED, YET
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output clk_en;
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output clk_en;
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output sample_point;
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output sampled_bit;
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output sampled_bit_q;
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input idle;
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reg [8:0] clk_cnt;
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reg [8:0] clk_cnt;
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reg clk_en;
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reg clk_en;
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reg sync_blocked;
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reg sync_blocked;
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reg sampled_bit;
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reg sampled_bit;
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reg sampled_bit_q;
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reg [7:0] quant_cnt;
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reg [7:0] quant_cnt;
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reg [3:0] delay;
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reg [3:0] delay;
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reg sync;
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reg sync;
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reg seg1;
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reg seg1;
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reg seg2;
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reg seg2;
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reg resync_latched;
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reg resync_latched;
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reg sample_pulse;
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reg sample_point;
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reg [1:0] sample;
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reg [1:0] sample;
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wire go_sync;
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wire go_sync;
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wire go_seg1;
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wire go_seg1;
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wire go_seg2;
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wire go_seg2;
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Line 152... |
wire sync_window;
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wire sync_window;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = idle & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization
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assign hard_sync = rx_idle & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization
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assign resync = (~idle) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
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assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
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/* Generating general enable signal that defines baud rate. */
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/* Generating general enable signal that defines baud rate. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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clk_cnt <= 0;
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clk_cnt <= 0;
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clk_en <= 1'b0;
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else if (clk_cnt == (preset_cnt-1) | reset_mode)
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clk_cnt <=#Tp 0;
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else
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clk_cnt <=#Tp clk_cnt + 1;
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end
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end
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else if (clk_cnt == (preset_cnt-1))
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always @ (posedge clk or posedge rst)
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begin
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begin
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clk_cnt <=#Tp 0;
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if (rst)
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clk_en <= 1'b0;
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else if (clk_cnt == (preset_cnt-1))
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clk_en <=#Tp 1'b1;
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clk_en <=#Tp 1'b1;
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end
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else
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else
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begin
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clk_cnt <=#Tp clk_cnt + 1;
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clk_en <=#Tp 1'b0;
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clk_en <=#Tp 1'b0;
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end
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end
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end
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/* Changing states */
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/* Changing states */
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//assign go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));
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assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));
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assign go_sync = clk_en & (seg2 & ((quant_cnt == time_segment2)));
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assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + delay)));
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assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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SJW is reached */
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SJW is reached */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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Line 205... |
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/* Synchronization stage/segment */
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/* Synchronization stage/segment */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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sync <= 1;
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sync <= 0;
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else if (go_sync)
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else if (go_sync)
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sync <=#Tp 1'b1;
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sync <=#Tp 1'b1;
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else if (go_seg1)
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else if (go_seg1)
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sync <=#Tp 1'b0;
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sync <=#Tp 1'b0;
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end
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end
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Line 217... |
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/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
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/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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seg1 <= 0;
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seg1 <= 1;
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else if (go_seg1)
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else if (go_seg1)
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seg1 <=#Tp 1'b1;
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seg1 <=#Tp 1'b1;
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else if (go_seg2)
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else if (go_seg2)
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seg1 <=#Tp 1'b0;
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seg1 <=#Tp 1'b0;
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end
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end
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Line 281... |
always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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sampled_bit <= 1;
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sampled_bit <= 1;
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sample_pulse <= 0;
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sampled_bit_q <= 1;
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sample_point <= 0;
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end
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end
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else if (clk_en)
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else if (clk_en)
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begin
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begin
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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begin
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begin
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sample_pulse <=#Tp 1;
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sample_point <=#Tp 1;
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sampled_bit_q <=#Tp sampled_bit;
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if (triple_sampling)
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if (triple_sampling)
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sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
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sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
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else
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else
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sampled_bit <=#Tp rx;
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sampled_bit <=#Tp rx;
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end
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end
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end
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end
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else
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else
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sample_pulse <=#Tp 0; // Sample pulse is for development purposes only. REMOVE ME.
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sample_point <=#Tp 0;
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end
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end
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/* Blocking synchronization (can occur only once in a bit time) */
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/* Blocking synchronization (can occur only once in a bit time) */
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