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Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.20 2003/06/20 14:51:11 mohor
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// Previous change removed. When resynchronization occurs we go to seg1
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// stage. sync stage does not cause another start of seg1 stage.
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//
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// Revision 1.19 2003/06/20 14:28:20 mohor
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// Revision 1.19 2003/06/20 14:28:20 mohor
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// When hard_sync or resync occure we need to go to seg1 segment. Going to
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// When hard_sync or resync occure we need to go to seg1 segment. Going to
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// sync segment is in that case blocked.
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// sync segment is in that case blocked.
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//
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//
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// Revision 1.18 2003/06/17 15:53:33 mohor
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// Revision 1.18 2003/06/17 15:53:33 mohor
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Line 148... |
tx_point,
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tx_point,
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hard_sync,
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hard_sync,
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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rx_idle,
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rx_idle,
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last_bit_of_inter
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last_bit_of_inter,
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transmitting,
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go_rx_inter
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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Line 175... |
input triple_sampling;
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input triple_sampling;
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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input rx_idle;
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input rx_idle;
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input last_bit_of_inter;
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input last_bit_of_inter;
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input transmitting;
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input go_rx_inter;
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/* Output signals from this module */
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/* Output signals from this module */
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output sample_point;
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output sample_point;
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output sampled_bit;
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output sampled_bit;
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output sampled_bit_q;
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output sampled_bit_q;
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| Line 187... |
Line 191... |
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reg [6:0] clk_cnt;
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reg [6:0] clk_cnt;
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reg clk_en;
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reg clk_en;
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reg clk_en_q;
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reg clk_en_q;
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reg sync_blocked;
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reg sync_blocked;
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reg resync_blocked;
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reg hard_sync_blocked;
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reg sampled_bit;
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reg sampled_bit;
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reg sampled_bit_q;
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reg sampled_bit_q;
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reg [4:0] quant_cnt;
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reg [4:0] quant_cnt;
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reg [3:0] delay;
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reg [3:0] delay;
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reg sync;
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reg sync;
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Line 203... |
reg seg2;
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reg seg2;
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reg resync_latched;
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reg resync_latched;
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reg sample_point;
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reg sample_point;
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reg [1:0] sample;
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reg [1:0] sample;
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reg go_sync;
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reg go_sync;
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reg go_seg1;
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reg go_seg2;
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reg tx_point;
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wire go_sync_unregistered;
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wire go_sync_unregistered;
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wire go_seg1;
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wire go_seg1_unregistered;
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wire go_seg2;
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wire go_seg2_unregistered;
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wire [8:0] preset_cnt;
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wire [8:0] preset_cnt;
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wire sync_window;
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wire sync_window;
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wire resync;
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wire resync;
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wire quant_cnt_rst;
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wire quant_cnt_rst;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
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assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked); // Re-synchronization
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assign resync = (~rx_idle) & (~last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~(transmitting & seg1)); // Re-synchronization
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/* Generating general enable signal that defines baud rate. */
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/* Generating general enable signal that defines baud rate. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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Line 258... |
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/* Changing states */
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/* Changing states */
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assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
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assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
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assign go_seg1 = clk_en_q & ((sync & (~seg1)) | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg1_unregistered = clk_en & (((sync | hard_sync) & (~seg1)) | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
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assign go_seg2_unregistered = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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Line 271... |
else
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else
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go_sync <=#Tp go_sync_unregistered;
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go_sync <=#Tp go_sync_unregistered;
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end
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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go_seg1 <= 1'b0;
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else
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go_seg1 <=#Tp go_seg1_unregistered;
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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go_seg2 <= 1'b0;
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else
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go_seg2 <=#Tp go_seg2_unregistered;
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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tx_point <= 1'b0;
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else
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tx_point <=#Tp go_sync_unregistered | (go_seg1_unregistered & (~(sync | hard_sync)));
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end
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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SJW is reached */
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SJW is reached */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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Line 324... |
else if (clk_en_q)
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else if (clk_en_q)
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sync <=#Tp 1'b0;
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sync <=#Tp 1'b0;
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end
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end
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assign tx_point = go_sync;
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/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
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/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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seg1 <= 1;
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seg1 <= 1;
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Line 423... |
begin
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begin
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if (rst)
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if (rst)
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sync_blocked <=#Tp 1'b0;
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sync_blocked <=#Tp 1'b0;
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else if (clk_en_q)
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else if (clk_en_q)
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begin
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begin
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if (hard_sync | resync)
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if (resync)
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sync_blocked <=#Tp 1'b1;
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sync_blocked <=#Tp 1'b1;
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else if (seg2 & (quant_cnt[2:0] == time_segment2))
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else if (seg2 & (quant_cnt[2:0] == time_segment2))
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sync_blocked <=#Tp 1'b0;
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sync_blocked <=#Tp 1'b0;
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end
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end
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end
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end
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/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for
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/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
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end-of-frame and interframe. No resynchronization is needed meanwhile). */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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resync_blocked <=#Tp 1'b1;
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hard_sync_blocked <=#Tp 1'b0;
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else if (reset_mode)
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else if (hard_sync | transmitting & tx_point)
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resync_blocked <=#Tp 1'b1;
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hard_sync_blocked <=#Tp 1'b1;
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else if (hard_sync)
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else if (go_rx_inter)
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resync_blocked <=#Tp 1'b0;
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hard_sync_blocked <=#Tp 1'b0;
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end
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end
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