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[/] [can/] [tags/] [rel_10/] [rtl/] [verilog/] [can_btl.v] - Diff between revs 11 and 15
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Rev 15 |
Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2003/01/08 02:10:53 mohor
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// Acceptance filter added.
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//
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// Revision 1.6 2002/12/28 04:13:23 mohor
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// Revision 1.6 2002/12/28 04:13:23 mohor
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// Backup version.
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// Backup version.
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//
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//
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// Revision 1.5 2002/12/27 00:12:52 mohor
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// Revision 1.5 2002/12/27 00:12:52 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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// Header changed, testbench improved to send a frame (crc still missing).
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Line 290... |
Line 293... |
begin
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begin
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sampled_bit <= 1;
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sampled_bit <= 1;
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sampled_bit_q <= 1;
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sampled_bit_q <= 1;
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sample_point <= 0;
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sample_point <= 0;
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end
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end
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else if (clk_en)
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else if (clk_en & (~hard_sync))
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begin
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begin
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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begin
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begin
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sample_point <=#Tp 1;
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sample_point <=#Tp 1;
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sampled_bit_q <=#Tp sampled_bit;
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sampled_bit_q <=#Tp sampled_bit;
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