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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Initial
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//
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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Line 117... |
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reg [8:0] clk_cnt;
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reg [8:0] clk_cnt;
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reg clk_en;
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reg clk_en;
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reg hard_sync_blocked;
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reg sync_blocked;
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reg resync_blocked;
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reg monitored_bit;
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reg monitored_bit;
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/* Needed for edge detection */
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/* Needed for edge detection */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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monitored_bit <= 1'b0;
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monitored_bit <= 1'b1;
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else if(clk_en)
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else if(clk_en)
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monitored_bit <=#Tp rx;
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monitored_bit <=#Tp rx;
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end
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end
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reg sampled_bit;
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reg sampled_bit;
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reg [7:0] quant_cnt;
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reg [7:0] quant_cnt;
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reg [3:0] dodatek;
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wire odstevek;
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wire [7:0] difference;
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reg rx_early;
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/* Generating general enable signal that defines baud rate.
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/* Generating general enable signal that defines baud rate.
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Hard synchronization is done here. */
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Hard synchronization is done here. */
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wire [8:0] preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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wire [8:0] preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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wire hard_sync = idle & (~monitored_bit) & sampled_bit & (~hard_sync_blocked);
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wire hard_sync = idle & (~rx) & sampled_bit & (~sync_blocked);
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wire resync = (~idle) & (~monitored_bit) & sampled_bit & (~resync_blocked);
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wire resync = (~idle) & (~rx) & sampled_bit & (~sync_blocked);
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/* Generating enable signal (can clock) */
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/* Generating enable signal (can clock) */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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Line 172... |
clk_en <=#Tp 1'b0;
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clk_en <=#Tp 1'b0;
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end
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end
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end
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end
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/* Hard Synchronization */
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assign difference = time_segment1 + time_segment2 + 3 - quant_cnt;
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/* Synchronization */
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/*
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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begin
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quant_cnt <=#Tp 0;
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sync_blocked <=#Tp 1'b0;
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dodatek <=#Tp 0;
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odstevek <=#Tp 0;
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end
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else if (clk_en)
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begin
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if (hard_sync) // Hard synchronization
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begin
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quant_cnt <=#Tp 1;
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sync_blocked <=#Tp 1'b1;
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end
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else if (resync) // resynchronization
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begin
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sync_blocked <=#Tp 1'b1;
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if (quant_cnt == 0) // Right on time
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quant_cnt <=#Tp quant_cnt + 1;
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else if (rx_early) // Too early
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begin
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quant_cnt <=#Tp 1;
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odstevek <=#Tp (difference > (sync_jump_width + 1))? (sync_jump_width + 1) : difference;
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end
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else // Too late // Take smaller (SJW : quant_cnt)
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begin
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dodatek <=#Tp (quant_cnt > (sync_jump_width + 1))? (sync_jump_width + 1) : quant_cnt;
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quant_cnt <=#Tp quant_cnt + 1;
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end
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end
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else if (quant_cnt == (time_segment1 + time_segment2 + 2 + dodatek))
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// else if (quant_cnt == (time_segment1 + time_segment2 + 2 + dodatek - odstevek))
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begin
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quant_cnt <=#Tp 0;
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sync_blocked <=#Tp 1'b0;
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dodatek <=#Tp 0;
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odstevek <=#Tp 0;
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end
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else
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quant_cnt <=#Tp quant_cnt + 1;
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end
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end
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reg sample_pulse;
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// Sampling data
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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begin
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sampled_bit <= 1;
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sample_pulse <= 0;
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end
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else if (clk_en & (quant_cnt == (time_segment1 + 1 + dodatek)) & (~idle)) // (~idle) blocks sampling so hard sync works in all cases
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begin
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sampled_bit <=#Tp rx;
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sample_pulse <=#Tp 1;
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end
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else
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sample_pulse <=#Tp 0;
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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begin
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rx_early <= 1'b0;
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end
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else if (clk_en & rx & (quant_cnt == (time_segment1 + 1)))
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begin
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rx_early <=#Tp 1'b1;
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end
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else if (clk_en & (quant_cnt == 0))
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rx_early <=#Tp 1'b0;
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end
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*/
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reg sync;
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reg seg1;
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reg seg2;
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reg resync_latched;
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wire go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));
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wire go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & odstevek) | (resync_latched & odstevek));
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wire go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + dodatek)));
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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resync_latched <= 1'b0;
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quant_cnt <=#Tp 0;
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else if (resync & seg2 & (~odstevek))
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hard_sync_blocked <=#Tp 1'b0;
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resync_latched <=#Tp 1'b1;
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else if (go_seg1)
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resync_latched <= 1'b0;
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end
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end
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else if (clk_en)
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begin
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if (hard_sync || (quant_cnt == (time_segment1 + time_segment2 + 2))) // Hard synchronization
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always @ (posedge clk or posedge rst)
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begin
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begin
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quant_cnt <=#Tp 0;
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if (rst)
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hard_sync_blocked <=#Tp hard_sync;
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sync <= 1;
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else if (go_sync)
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sync <=#Tp 1'b1;
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else if (go_seg1)
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sync <=#Tp 1'b0;
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end
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end
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else
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always @ (posedge clk or posedge rst)
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begin
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begin
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quant_cnt <=#Tp quant_cnt + 1;
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if (rst)
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end
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seg1 <= 0;
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end
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else if (go_seg1)
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seg1 <=#Tp 1'b1;
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else if (go_seg2)
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seg1 <=#Tp 1'b0;
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end
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end
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/* Resynchronization */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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seg2 <= 0;
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resync_blocked <=#Tp 1'b0;
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else if (go_seg2)
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seg2 <=#Tp 1'b1;
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else if (go_sync | go_seg1)
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seg2 <=#Tp 1'b0;
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end
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end
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else if (clk_en)
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begin
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if (resync)
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begin
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if (quant_cnt == (time_segment1 + time_segment2 + 2)) // Right on time
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dodatek = 0;
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else if (sample_point_passed) // Too late
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dodatek = quant_cnt; // Take smaller (SJW : quant_cnt)
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else // Too early
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reseti clock to 0 so we start with new bit sooner
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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quant_cnt <= 0;
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else if (go_sync || go_seg1 || go_seg2)
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quant_cnt <=#Tp 0;
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else if (clk_en)
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quant_cnt <=#Tp quant_cnt + 1'b1;
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end
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/* sample_point_passed is needed for phase error detection. Signal is set only when resynchronization is possible (high to low transition) */
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always @ (posedge clk or posedge rst)
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reg sample_point_passed;
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always @ (posedge clk)
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begin
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if (clk_en & (quant_cnt == (time_segment1 + time_segment2 + 2)))
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begin
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begin
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if(rx)
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if (rst)
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sample_point_passed <=#Tp 1'b0;
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dodatek <= 0;
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else
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else if (clk_en & resync & seg1)
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sample_point_passed <=#Tp 1'b1;
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dodatek <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);
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end
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else if (go_sync | go_seg1)
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end
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dodatek <=#Tp 0;
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end
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/*
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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odstevek <= 0;
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else if (clk_en & resync & seg2)
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odstevek <=#Tp ((time_segment2 + 1 - quant_cnt) > sync_jump_width)? (sync_jump_width + 1) : (time_segment2 + 1 - quant_cnt);
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else if (go_sync | go_seg1)
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odstevek <=#Tp 0;
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end
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*/
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assign odstevek = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
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/* Sampling data */
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wire sample_time =
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reg sample_pulse;
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// Sampling data
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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sampled_bit <= 1;
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sampled_bit <= 1;
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sample_pulse <= 0;
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end
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end
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else if (clk_en & (quant_cnt == time_segment1))
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else if (go_seg2)
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begin
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begin
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sampled_bit <=#Tp rx;
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sampled_bit <=#Tp rx;
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sample_pulse <=#Tp 1;
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end
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end
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else
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sample_pulse <=#Tp 0;
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end
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end
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Detect phase error and change the above flip-flop
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/* Blocking synchronization (can occur only once in a bit time) */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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sync_blocked <=#Tp 1'b0;
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else if (clk_en)
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begin
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if (hard_sync || resync)
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sync_blocked <=#Tp 1'b1;
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else if (seg2 & quant_cnt == time_segment2)
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sync_blocked <=#Tp 1'b0;
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end
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end
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endmodule
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endmodule
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