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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/12/25 23:44:16 mohor
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// Commented lines removed.
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//
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// Revision 1.2 2002/12/25 14:17:00 mohor
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// Revision 1.2 2002/12/25 14:17:00 mohor
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// Synchronization working.
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// Synchronization working.
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//
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//
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Initial
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// Initial
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Line 110... |
input [3:0] time_segment1;
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input [3:0] time_segment1;
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input [2:0] time_segment2;
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input [2:0] time_segment2;
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input triple_sampling;
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input triple_sampling;
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/* Output signals from this module */
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/* Output signals from this module */
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output take_sample;
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output take_sample; // NOT USED, YET
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output clk_en;
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output clk_en;
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input idle;
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input idle;
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/* bit stream processor (can_bsp.v) */
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/* bit stream processor (can_bsp.v) */
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Line 130... |
reg sync;
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reg sync;
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reg seg1;
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reg seg1;
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reg seg2;
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reg seg2;
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reg resync_latched;
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reg resync_latched;
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reg sample_pulse;
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reg sample_pulse;
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reg [1:0] sample;
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wire go_sync;
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wire go_sync;
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wire go_seg1;
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wire go_seg1;
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wire go_seg2;
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wire go_seg2;
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wire [8:0] preset_cnt;
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wire [8:0] preset_cnt;
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Line 170... |
end
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end
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/* Changing states */
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/* Changing states */
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assign go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));
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//assign go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));
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assign go_sync = clk_en & (seg2 & ((quant_cnt == time_segment2)));
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assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + delay)));
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assign go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + delay)));
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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Line 254... |
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// If early edge appears within this window (in seg2 stage), phase error is fully compensated
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// If early edge appears within this window (in seg2 stage), phase error is fully compensated
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assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
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assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
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// Sampling data
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// Sampling data (memorizing two samples all the time).
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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sample <= 2'b11;
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else if (clk_en)
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sample <= {sample[0], rx};
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end
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// When enabled, tripple sampling is done here.
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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sampled_bit <= 1;
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sampled_bit <= 1;
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sample_pulse <= 0;
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sample_pulse <= 0;
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end
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end
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else if (go_seg2)
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else if (clk_en)
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begin
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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begin
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begin
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sampled_bit <=#Tp rx;
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sample_pulse <=#Tp 1;
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sample_pulse <=#Tp 1;
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if (triple_sampling)
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sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
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else
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sampled_bit <=#Tp rx;
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end
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end
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end
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else
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else
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sample_pulse <=#Tp 0; // Sample pulse is for development purposes only. REMOVE ME.
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sample_pulse <=#Tp 0; // Sample pulse is for development purposes only. REMOVE ME.
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end
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end
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