| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2003/02/14 20:17:01 mohor
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// Several registers added. Not finished, yet.
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//
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// Revision 1.11 2003/02/09 18:40:29 mohor
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// Revision 1.11 2003/02/09 18:40:29 mohor
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// Overload fixed. Hard synchronization also enabled at the last bit of
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// Overload fixed. Hard synchronization also enabled at the last bit of
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// interframe.
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// interframe.
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//
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//
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// Revision 1.10 2003/02/09 02:24:33 mohor
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// Revision 1.10 2003/02/09 02:24:33 mohor
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| Line 116... |
Line 119... |
sample_point,
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sample_point,
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sampled_bit,
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sampled_bit,
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sampled_bit_q,
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sampled_bit_q,
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tx_point,
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tx_point,
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hard_sync,
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hard_sync,
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resync,
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go_seg1,
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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rx_idle,
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rx_idle,
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transmitting,
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transmitting,
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overjump_sync_seg,
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last_bit_of_inter
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last_bit_of_inter
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| Line 150... |
Line 154... |
input triple_sampling;
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input triple_sampling;
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/* Output from can_bsp module */
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/* Output from can_bsp module */
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input rx_idle;
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input rx_idle;
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input transmitting;
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input transmitting;
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input overjump_sync_seg;
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input last_bit_of_inter;
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input last_bit_of_inter;
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/* Output signals from this module */
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/* Output signals from this module */
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output clk_en;
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output clk_en;
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output sample_point;
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output sample_point;
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output sampled_bit;
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output sampled_bit;
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output sampled_bit_q;
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output sampled_bit_q;
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output tx_point;
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output tx_point;
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output hard_sync;
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output hard_sync;
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output resync;
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output go_seg1;
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reg [8:0] clk_cnt;
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reg [8:0] clk_cnt;
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reg clk_en;
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reg clk_en;
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| Line 183... |
Line 188... |
wire go_sync;
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wire go_sync;
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wire go_seg1;
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wire go_seg1;
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wire go_seg2;
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wire go_seg2;
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wire [8:0] preset_cnt;
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wire [8:0] preset_cnt;
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wire sync_window;
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wire sync_window;
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wire resync;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization
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assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization
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assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization
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Line 284... |
/* Quant counter */
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/* Quant counter */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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quant_cnt <= 0;
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quant_cnt <= 0;
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else if (go_sync | go_seg1 | go_seg2)
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else if (go_sync | go_seg1 & (~overjump_sync_seg) | go_seg2)
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quant_cnt <=#Tp 0;
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quant_cnt <=#Tp 0;
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else if (go_seg1 & overjump_sync_seg)
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quant_cnt <=#Tp 1;
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else if (clk_en)
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else if (clk_en)
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quant_cnt <=#Tp quant_cnt + 1'b1;
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quant_cnt <=#Tp quant_cnt + 1'b1;
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end
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end
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