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Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2003/06/11 14:21:35 mohor
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// When switching to tx, sync stage is overjumped.
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//
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// Revision 1.12 2003/02/14 20:17:01 mohor
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// Revision 1.12 2003/02/14 20:17:01 mohor
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// Several registers added. Not finished, yet.
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// Several registers added. Not finished, yet.
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//
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//
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// Revision 1.11 2003/02/09 18:40:29 mohor
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// Revision 1.11 2003/02/09 18:40:29 mohor
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// Overload fixed. Hard synchronization also enabled at the last bit of
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// Overload fixed. Hard synchronization also enabled at the last bit of
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| Line 174... |
Line 177... |
reg clk_en;
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reg clk_en;
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reg sync_blocked;
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reg sync_blocked;
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reg resync_blocked;
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reg resync_blocked;
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reg sampled_bit;
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reg sampled_bit;
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reg sampled_bit_q;
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reg sampled_bit_q;
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reg [7:0] quant_cnt;
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reg [4:0] quant_cnt;
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reg [3:0] delay;
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reg [3:0] delay;
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reg sync;
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reg sync;
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reg seg1;
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reg seg1;
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reg seg2;
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reg seg2;
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reg resync_latched;
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reg resync_latched;
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reg sample_point;
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reg sample_point;
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reg [1:0] sample;
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reg [1:0] sample;
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reg go_sync;
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wire go_sync;
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wire go_sync_unregistered;
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wire go_seg1;
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wire go_seg1;
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wire go_seg2;
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wire go_seg2;
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wire [8:0] preset_cnt;
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wire [8:0] preset_cnt;
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wire sync_window;
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wire sync_window;
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wire resync;
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wire resync;
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wire quant_cnt_rst1;
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wire quant_cnt_rst2;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization
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assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization
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assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization
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assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization
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Line 208... |
/* Generating general enable signal that defines baud rate. */
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/* Generating general enable signal that defines baud rate. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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clk_cnt <= 0;
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clk_cnt <= 0;
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else if (clk_cnt == (preset_cnt-1))
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else if (clk_cnt == (preset_cnt-1'b1))
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clk_cnt <=#Tp 0;
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clk_cnt <=#Tp 0;
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else
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else
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clk_cnt <=#Tp clk_cnt + 1;
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clk_cnt <=#Tp clk_cnt + 1'b1;
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end
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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clk_en <= 1'b0;
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clk_en <= 1'b0;
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else if (clk_cnt == (preset_cnt-1))
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else if (clk_cnt == (preset_cnt-1'b1))
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clk_en <=#Tp 1'b1;
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clk_en <=#Tp 1'b1;
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else
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else
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clk_en <=#Tp 1'b0;
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clk_en <=#Tp 1'b0;
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end
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end
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/* Changing states */
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/* Changing states */
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assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));
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assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
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assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
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assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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go_sync <= 1'b0;
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else
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go_sync <=#Tp go_sync_unregistered;
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end
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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SJW is reached */
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SJW is reached */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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| Line 248... |
Line 264... |
begin
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begin
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if (rst)
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if (rst)
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sync <= 0;
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sync <= 0;
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else if (go_sync)
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else if (go_sync)
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sync <=#Tp 1'b1;
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sync <=#Tp 1'b1;
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else if (go_seg1)
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else
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sync <=#Tp 1'b0;
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sync <=#Tp 1'b0;
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end
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end
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assign tx_point = go_sync;
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assign tx_point = go_sync;
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Line 296... |
seg2 <=#Tp 1'b0;
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seg2 <=#Tp 1'b0;
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end
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end
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/* Quant counter */
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/* Quant counter */
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assign quant_cnt_rst1 = go_sync | go_seg1 & (~overjump_sync_seg) | go_seg2;
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assign quant_cnt_rst2 = go_seg1 & overjump_sync_seg;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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quant_cnt <= 0;
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quant_cnt <= 0;
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else if (go_sync | go_seg1 & (~overjump_sync_seg) | go_seg2)
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else if (quant_cnt_rst1)
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quant_cnt <=#Tp 0;
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quant_cnt <=#Tp 0;
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else if (go_seg1 & overjump_sync_seg)
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else if (quant_cnt_rst2)
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quant_cnt <=#Tp 1;
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quant_cnt <=#Tp 1;
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else if (clk_en)
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else if (clk_en)
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quant_cnt <=#Tp quant_cnt + 1'b1;
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quant_cnt <=#Tp quant_cnt + 1'b1;
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end
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end
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Line 318... |
always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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delay <= 0;
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delay <= 0;
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else if (clk_en & resync & seg1)
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else if (clk_en & resync & seg1)
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delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);
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delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
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else if (go_sync | go_seg1)
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else if (go_sync | go_seg1)
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delay <=#Tp 0;
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delay <=#Tp 0;
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end
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end
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// If early edge appears within this window (in seg2 stage), phase error is fully compensated
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// If early edge appears within this window (in seg2 stage), phase error is fully compensated
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assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
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assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
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// Sampling data (memorizing two samples all the time).
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// Sampling data (memorizing two samples all the time).
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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Line 375... |
sync_blocked <=#Tp 1'b0;
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sync_blocked <=#Tp 1'b0;
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else if (clk_en)
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else if (clk_en)
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begin
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begin
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if (hard_sync | resync)
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if (hard_sync | resync)
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sync_blocked <=#Tp 1'b1;
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sync_blocked <=#Tp 1'b1;
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else if (seg2 & quant_cnt == time_segment2)
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else if (seg2 & (quant_cnt[2:0] == time_segment2))
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sync_blocked <=#Tp 1'b0;
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sync_blocked <=#Tp 1'b0;
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end
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end
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end
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end
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