| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2003/06/13 15:02:24 mohor
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// Synchronization is also needed when transmitting a message.
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//
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// Revision 1.14 2003/06/13 14:55:11 mohor
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// Revision 1.14 2003/06/13 14:55:11 mohor
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// Counters width changed.
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// Counters width changed.
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//
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//
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// Revision 1.13 2003/06/11 14:21:35 mohor
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// Revision 1.13 2003/06/11 14:21:35 mohor
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// When switching to tx, sync stage is overjumped.
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// When switching to tx, sync stage is overjumped.
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| Line 119... |
Line 122... |
time_segment1,
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time_segment1,
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time_segment2,
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time_segment2,
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triple_sampling,
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triple_sampling,
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/* Output signals from this module */
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/* Output signals from this module */
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clk_en,
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sample_point,
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sample_point,
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sampled_bit,
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sampled_bit,
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sampled_bit_q,
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sampled_bit_q,
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tx_point,
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tx_point,
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hard_sync,
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hard_sync,
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| Line 162... |
Line 164... |
input rx_idle;
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input rx_idle;
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input overjump_sync_seg;
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input overjump_sync_seg;
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input last_bit_of_inter;
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input last_bit_of_inter;
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/* Output signals from this module */
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/* Output signals from this module */
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output clk_en;
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output sample_point;
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output sample_point;
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output sampled_bit;
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output sampled_bit;
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output sampled_bit_q;
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output sampled_bit_q;
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output tx_point;
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output tx_point;
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output hard_sync;
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output hard_sync;
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| Line 174... |
Line 175... |
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reg [8:0] clk_cnt;
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reg [8:0] clk_cnt;
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reg clk_en;
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reg clk_en;
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reg clk_en_q;
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reg sync_blocked;
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reg sync_blocked;
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reg resync_blocked;
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reg resync_blocked;
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reg sampled_bit;
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reg sampled_bit;
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reg sampled_bit_q;
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reg sampled_bit_q;
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reg [4:0] quant_cnt;
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reg [4:0] quant_cnt;
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| Line 209... |
Line 211... |
/* Generating general enable signal that defines baud rate. */
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/* Generating general enable signal that defines baud rate. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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clk_cnt <= 0;
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clk_cnt <= 0;
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else if (clk_cnt == (preset_cnt-1'b1))
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else if (clk_cnt >= (preset_cnt-1'b1))
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clk_cnt <=#Tp 0;
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clk_cnt <=#Tp 0;
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else
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else
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clk_cnt <=#Tp clk_cnt + 1'b1;
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clk_cnt <=#Tp clk_cnt + 1'b1;
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end
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end
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| Line 228... |
Line 230... |
clk_en <=#Tp 1'b0;
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clk_en <=#Tp 1'b0;
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end
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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clk_en_q <= 1'b0;
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else
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clk_en_q <=#Tp clk_en;
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end
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/* Changing states */
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/* Changing states */
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assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
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assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
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assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg1 = clk_en_q & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
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assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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| Line 265... |
Line 276... |
begin
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begin
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if (rst)
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if (rst)
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sync <= 0;
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sync <= 0;
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else if (go_sync)
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else if (go_sync)
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sync <=#Tp 1'b1;
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sync <=#Tp 1'b1;
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else
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else if (clk_en_q)
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sync <=#Tp 1'b0;
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sync <=#Tp 1'b0;
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end
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end
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assign tx_point = go_sync;
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assign tx_point = go_sync;
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| Line 298... |
Line 309... |
end
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end
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/* Quant counter */
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/* Quant counter */
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assign quant_cnt_rst1 = go_sync | go_seg1 & (~overjump_sync_seg) | go_seg2;
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//assign quant_cnt_rst1 = go_sync | go_seg1 & (~overjump_sync_seg) | go_seg2;
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assign quant_cnt_rst2 = go_seg1 & overjump_sync_seg;
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//assign quant_cnt_rst2 = go_seg1 & overjump_sync_seg;
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assign quant_cnt_rst1 = go_sync | go_seg1 | go_seg2;
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assign quant_cnt_rst2 = 1'b0;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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quant_cnt <= 0;
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quant_cnt <= 0;
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else if (quant_cnt_rst1)
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else if (quant_cnt_rst1)
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quant_cnt <=#Tp 0;
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quant_cnt <=#Tp 0;
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else if (quant_cnt_rst2)
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else if (quant_cnt_rst2)
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quant_cnt <=#Tp 1;
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quant_cnt <=#Tp 1;
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else if (clk_en)
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else if (clk_en_q)
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quant_cnt <=#Tp quant_cnt + 1'b1;
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quant_cnt <=#Tp quant_cnt + 1'b1;
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end
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end
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/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
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/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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delay <= 0;
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delay <= 0;
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else if (clk_en & resync & seg1)
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else if (clk_en_q & resync & seg1)
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delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
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delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
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else if (go_sync | go_seg1)
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else if (go_sync | go_seg1)
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delay <=#Tp 0;
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delay <=#Tp 0;
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end
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end
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| Line 334... |
Line 347... |
// Sampling data (memorizing two samples all the time).
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// Sampling data (memorizing two samples all the time).
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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sample <= 2'b11;
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sample <= 2'b11;
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else if (clk_en)
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else if (clk_en_q)
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sample <= {sample[0], rx};
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sample <= {sample[0], rx};
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end
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end
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// When enabled, tripple sampling is done here.
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// When enabled, tripple sampling is done here.
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| Line 348... |
Line 361... |
begin
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begin
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sampled_bit <= 1;
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sampled_bit <= 1;
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sampled_bit_q <= 1;
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sampled_bit_q <= 1;
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sample_point <= 0;
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sample_point <= 0;
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end
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end
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else if (clk_en & (~hard_sync))
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else if (clk_en_q & (~hard_sync))
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begin
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begin
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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begin
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begin
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sample_point <=#Tp 1;
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sample_point <=#Tp 1;
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sampled_bit_q <=#Tp sampled_bit;
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sampled_bit_q <=#Tp sampled_bit;
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| Line 372... |
Line 385... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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sync_blocked <=#Tp 1'b0;
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sync_blocked <=#Tp 1'b0;
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else if (clk_en)
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else if (clk_en_q)
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begin
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begin
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if (hard_sync | resync)
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if (hard_sync | resync)
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sync_blocked <=#Tp 1'b1;
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sync_blocked <=#Tp 1'b1;
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else if (seg2 & (quant_cnt[2:0] == time_segment2))
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else if (seg2 & (quant_cnt[2:0] == time_segment2))
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sync_blocked <=#Tp 1'b0;
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sync_blocked <=#Tp 1'b0;
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