URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_10/] [rtl/] [verilog/] [can_defines.v] - Diff between revs 51 and 59

Rev 51	Rev 59
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2003/03/05 15:03:20 mohor`
	`// Xilinx RAM added.`
	`//`
`// Revision 1.4 2003/03/01 22:52:47 mohor`	`// Revision 1.4 2003/03/01 22:52:47 mohor`
`// Actel APA ram supported.`	`// Actel APA ram supported.`
`//`	`//`
`// Revision 1.3 2003/02/09 02:24:33 mohor`	`// Revision 1.3 2003/02/09 02:24:33 mohor`
`// Bosch license warning added. Error counters finished. Overload frames`	`// Bosch license warning added. Error counters finished. Overload frames`
Line 65...	Line 68...
`//`	`//`
`//`	`//`
`//`	`//`


	`// Uncomment following line if you want to use WISHBONE interface. Otherwise`
	`// 8051 interface is used.`
	// `define CAN_WISHBONE_IF

`// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)`	`// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)`
// `define ACTEL_APA_RAM	// `define ACTEL_APA_RAM

`// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)`	`// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)`
// `define XILINX_RAM	// `define XILINX_RAM