| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.37 2003/06/27 20:56:15 simons
|
|
// Virtual silicon ram instances added.
|
|
//
|
// Revision 1.36 2003/06/17 14:30:30 mohor
|
// Revision 1.36 2003/06/17 14:30:30 mohor
|
// "chip select" signal cs_can_i is used only when not using WISHBONE
|
// "chip select" signal cs_can_i is used only when not using WISHBONE
|
// interface.
|
// interface.
|
//
|
//
|
// Revision 1.35 2003/06/16 13:57:58 mohor
|
// Revision 1.35 2003/06/16 13:57:58 mohor
|
| Line 537... |
Line 540... |
.hard_sync(hard_sync),
|
.hard_sync(hard_sync),
|
|
|
|
|
/* output from can_bsp module */
|
/* output from can_bsp module */
|
.rx_idle(rx_idle),
|
.rx_idle(rx_idle),
|
.last_bit_of_inter(last_bit_of_inter)
|
.last_bit_of_inter(last_bit_of_inter),
|
|
.transmitting(transmitting),
|
|
.go_rx_inter(go_rx_inter)
|
|
|
|
|
|
|
);
|
);
|
|
|
| Line 597... |
Line 602... |
.extended_mode(extended_mode),
|
.extended_mode(extended_mode),
|
|
|
/* output from can_bsp module */
|
/* output from can_bsp module */
|
.rx_idle(rx_idle),
|
.rx_idle(rx_idle),
|
.transmitting(transmitting),
|
.transmitting(transmitting),
|
|
.go_rx_inter(go_rx_inter),
|
.last_bit_of_inter(last_bit_of_inter),
|
.last_bit_of_inter(last_bit_of_inter),
|
.set_reset_mode(set_reset_mode),
|
.set_reset_mode(set_reset_mode),
|
.node_bus_off(node_bus_off),
|
.node_bus_off(node_bus_off),
|
.error_status(error_status),
|
.error_status(error_status),
|
.rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}), // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
|
.rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}), // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
|
