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https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [tags/] [rel_10/] [rtl/] [verilog/] [can_top.v] - Diff between revs 67 and 71
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| Rev 67 |
Rev 71 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.31 2003/03/26 11:19:46 mohor
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// CAN interrupt is active low.
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//
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// Revision 1.30 2003/03/20 17:01:17 mohor
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// Revision 1.30 2003/03/20 17:01:17 mohor
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// unix.
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// unix.
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//
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//
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// Revision 1.28 2003/03/14 19:36:48 mohor
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// Revision 1.28 2003/03/14 19:36:48 mohor
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// can_cs signal used for generation of the cs.
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// can_cs signal used for generation of the cs.
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| Line 178... |
Line 181... |
clk_i,
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clk_i,
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rx_i,
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rx_i,
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tx_o,
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tx_o,
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irq_on,
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irq_on,
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clkout_o
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clkout_o
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// Bist
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`ifdef CAN_BIST
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,
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// debug chain signals
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scanb_rst, // bist scan reset
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scanb_clk, // bist scan clock
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scanb_si, // bist scan serial in
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scanb_so, // bist scan serial out
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scanb_en // bist scan shift enable
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`endif
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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`ifdef CAN_WISHBONE_IF
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`ifdef CAN_WISHBONE_IF
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Line 235... |
input rx_i;
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input rx_i;
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output tx_o;
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output tx_o;
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output irq_on;
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output irq_on;
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output clkout_o;
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output clkout_o;
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// Bist
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`ifdef CAN_BIST
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input scanb_rst; // bist scan reset
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input scanb_clk; // bist scan clock
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input scanb_si; // bist scan serial in
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output scanb_so; // bist scan serial out
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input scanb_en; // bist scan shift enable
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`endif
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reg data_out_fifo_selected;
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reg data_out_fifo_selected;
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wire irq_o;
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wire irq_o;
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wire [7:0] data_out_fifo;
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wire [7:0] data_out_fifo;
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